===== 05 DLY CPU DELAYS | BIOS 19951204 System ROM Version 3.0 11/18/96 A

cpu/delays
lw 2 over 1: in the delay 00000001, after 00000002
lw 2 then li 5 in the delay: 00000005
lw 2 then lw 3: 00000001 00000003 00000003
mfc0 SR over 1: in the delay 00000001, after 00000401
mtc0 BDA then mfc0 at once: 12345678, after clearing 00000000
mtc2 00050006 then mfc2 over 1: 00000001 00000000 00000000
jal: ra - jal 8
beq in a beq's delay slot: 00001001 (1 and 16 from the first target, 256 and 4096 from the second)
Done.