===== 11 TMR TIMERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A timers test Detected NTSC system. Forced NTSC system. Timer0, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer0, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer0, clock: System clock, frame delay: 106570, 107323, 107359, 107321, 107348, 107305, 107330, 107352, 107316, 107346, Timer0, clock: Dot clock, 1000 cycles delay: 200, 200, 199, 200, 200, 201, 200, 200, 200, 200, Timer0, clock: Dot clock, 5000 cycles delay: 992, 992, 991, 992, 992, 991, 992, 992, 991, 991, Timer0, clock: Dot clock, frame delay: 111951, 112027, 112031, 112031, 112032, 112029, 112028, 112031, 112028, 112033, Timer1, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer1, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer1, clock: System clock, frame delay: 106925, 107332, 107354, 107316, 107339, 107319, 107366, 107325, 107306, 107359, Timer1, clock: Hblank, 1000 cycles delay: 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, Timer1, clock: Hblank, 5000 cycles delay: 3, 2, 2, 3, 2, 2, 3, 2, 2, 3, Timer1, clock: Hblank, frame delay: 263, 263, 263, 263, 263, 263, 263, 263, 263, 263, Timer2, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer2, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer2, clock: System clock, frame delay: 106919, 107319, 107346, 107319, 107358, 107345, 107329, 107305, 107354, 107323, Timer2, clock: System clock/8, 1000 cycles delay: 126, 127, 126, 126, 127, 126, 127, 126, 126, 127, Timer2, clock: System clock/8, 5000 cycles delay: 626, 627, 626, 626, 627, 626, 627, 626, 626, 627, Timer2, clock: System clock/8, frame delay: 70708, 70761, 70758, 70759, 70763, 70758, 70762, 70756, 70760, 70762, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs) 0 = Pause counter during Hblanks 311, 433, 555, 677, 799, 921, 1043, 1165, 1287, 1409, 1 = Reset counter to 0 at Hblanks 198, 320, 442, 564, 686, 808, 930, 1052, 1174, 1296, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 240, 362, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 19, 141, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs) 0 = Pause counter during Hblanks 285, 407, 529, 651, 773, 895, 1002, 1002, 1002, 1002, 1 = Reset counter to 0 at Hblanks 240, 362, 77, 199, 321, 443, 565, 687, 809, 931, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs) 0 = Pause counter during Hblanks 285, 407, 529, 651, 715, 715, 715, 715, 803, 925, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 31, 153, 275, 397, 519, 641, 763, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs) 0 = Pause counter during Hblanks 285, 407, 529, 651, 773, 895, 1017, 1139, 1261, 1344, 1 = Reset counter to 0 at Hblanks 235, 357, 479, 601, 723, 845, 967, 1089, 1211, 1333, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 89, 211, 333, 455, 577, 699, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs) 0 = Pause counter during Hblanks 0, 13, 135, 257, 379, 501, 623, 745, 867, 989, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 107, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs) 0 = Pause counter during Hblanks 42, 61, 81, 100, 119, 139, 158, 177, 197, 216, 1 = Reset counter to 0 at Hblanks 37, 57, 76, 95, 115, 134, 16, 36, 55, 74, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 12, 31, 50, 70, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs) 0 = Pause counter during Hblanks 56, 81, 85, 85, 85, 85, 95, 119, 143, 167, 1 = Reset counter to 0 at Hblanks 47, 71, 95, 119, 5, 29, 54, 78, 102, 126, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 42, 66, 90, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 5, 29, 53, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs) 0 = Pause counter during Hblanks 64, 92, 120, 147, 175, 202, 230, 258, 285, 313, 1 = Reset counter to 0 at Hblanks 54, 82, 109, 136, 164, 9, 36, 64, 92, 119, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 7, 34, 62, 89, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 50, 78, 105, 133, 161, 188, 216, 244, 271, 299, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs) 0 = Pause counter during Hblanks 67, 106, 145, 184, 222, 261, 300, 338, 377, 416, 1 = Reset counter to 0 at Hblanks 75, 114, 153, 191, 230, 269, 307, 346, 384, 423, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 27, 65, 104, 142, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs) 0 = Pause counter during Hblanks 113, 161, 210, 258, 289, 289, 289, 289, 289, 334, 1 = Reset counter to 0 at Hblanks 94, 143, 43, 91, 140, 188, 236, 285, 333, 381, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 22, 70, 118, 167, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 32, 81, 129, 178, 226, 274, 323, Testing Timer1 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Pause counter during Vblanks 285, 407, 529, 651, 773, 895, 1017, 1139, 1261, 1383, 1 = Reset counter to 0 at Vblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Vblanks and pause outside of Vblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Vblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer1 sync modes (clock source = Hblank, 100 delay cycles, not resetted between runs) 0 = Pause counter during Vblanks 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 = Reset counter to 0 at Vblanks 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2 = Reset counter to 0 at Vblanks and pause outside of Vblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Vblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 = Free Run 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Free Run 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 3 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 = Free Run 239, 361, 483, 605, 727, 849, 971, 1093, 1215, 1337, 2 = Free Run 239, 361, 483, 605, 727, 849, 971, 1093, 1215, 1337, 3 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Check when Timer2 counter (System clock) is reset when reaching target (= 10). counter == 0, 1665 ticks counter == 1, 835 ticks counter == 2, 833 ticks counter == 3, 831 ticks counter == 4, 836 ticks counter == 5, 834 ticks counter == 6, 831 ticks counter == 7, 835 ticks counter == 8, 834 ticks counter == 9, 831 ticks counter == 10, 835 ticks <<<< This value should be non-zero counter == 11, 0 ticks Reached target: 1 (ok) Reached 0xFFFF: 0 (ok) Counter reset AFTER reaching target: 1 (ok) Target + 1 not reached: 1 (ok) Check if write to mode register acknowledges the targetReached flag Write 0x0000 to Timer0.mode, read 0x0400 Write 0xffff to Timer0.mode, read 0x07ff Read mode after waiting for targetReached: 0x1c08 Read again: 0x0408 Write mode after waiting for targetReached and then read: 0x1c08 Read again: 0x0408 Done.