===== 06 TIM CPU MULT DIV TIME | BIOS 19951204 System ROM Version 3.0 11/18/96 A

cpu/mult div timing (timer 2, system clock)
nop   00000000 00000000: 547 cycles for 100
nop, 20 nops 00000000 00000000: 2576 cycles for 100
mult  00000000 00000003: 1147 cycles for 100
multu 00000000 00000003: 1147 cycles for 100
mult rt 00000003 00000000: 1127 cycles for 100
mult  00000001 00000003: 1127 cycles for 100
multu 00000001 00000003: 1135 cycles for 100
mult rt 00000003 00000001: 1127 cycles for 100
mult  000007FF 00000003: 1127 cycles for 100
multu 000007FF 00000003: 1135 cycles for 100
mult rt 00000003 000007FF: 1127 cycles for 100
mult  00000800 00000003: 1427 cycles for 100
multu 00000800 00000003: 1435 cycles for 100
mult rt 00000003 00000800: 1127 cycles for 100
mult  000FFFFF 00000003: 1427 cycles for 100
multu 000FFFFF 00000003: 1435 cycles for 100
mult rt 00000003 000FFFFF: 1127 cycles for 100
mult  00100000 00000003: 1827 cycles for 100
multu 00100000 00000003: 1835 cycles for 100
mult rt 00000003 00100000: 1127 cycles for 100
mult  7FFFFFFF 00000003: 1827 cycles for 100
multu 7FFFFFFF 00000003: 1835 cycles for 100
mult rt 00000003 7FFFFFFF: 1127 cycles for 100
mult  FFFFFFFF 00000003: 1153 cycles for 100
multu FFFFFFFF 00000003: 1842 cycles for 100
mult rt 00000003 FFFFFFFF: 1127 cycles for 100
mult  80000000 00000003: 1827 cycles for 100
multu 80000000 00000003: 1835 cycles for 100
mult rt 00000003 80000000: 1127 cycles for 100
div   12345678 00000003: 4147 cycles for 100
divu  12345678 00000003: 4147 cycles for 100
div by 0 12345678 00000000: 4132 cycles for 100
mult, 20 nops 7FFFFFFF 00000003: 2576 cycles for 100
div, 20 nops 12345678 00000003: 4156 cycles for 100
mult 00100000 00000003 then n nops then mflo:
mult, 0 nops, mflo: 1847 cycles for 100
mult, 1 nops, mflo: 1848 cycles for 100
mult, 2 nops, mflo: 1850 cycles for 100
mult, 3 nops, mflo: 1853 cycles for 100
mult, 4 nops, mflo: 1853 cycles for 100
mult, 5 nops, mflo: 1859 cycles for 100
mult, 6 nops, mflo: 1860 cycles for 100
mult, 7 nops, mflo: 1858 cycles for 100
mult, 8 nops, mflo: 1852 cycles for 100
mult, 9 nops, mflo: 1861 cycles for 100
mult, 10 nops, mflo: 1862 cycles for 100
mult, 11 nops, mflo: 1860 cycles for 100
mult, 12 nops, mflo: 1771 cycles for 100
mult, 13 nops, mflo: 1873 cycles for 100
mult, 14 nops, mflo: 1976 cycles for 100
div, 5 nops, mflo: 4143 cycles for 100
div, 10 nops, mflo: 4147 cycles for 100
div, 30 nops, mflo: 4181 cycles for 100
div, 33 nops, mflo: 4185 cycles for 100
div, 34 nops, mflo: 4193 cycles for 100
div, 35 nops, mflo: 4088 cycles for 100
div, 36 nops, mflo: 4192 cycles for 100
div, 37 nops, mflo: 4300 cycles for 100
what waits for a busy multiply (rs 00100000):
mult then mfhi: 1849 cycles for 100
mult, no read: 448 cycles for 100
div, no read: 448 cycles for 100
mult then mtlo: 558 cycles for 100
mult then mthi: 554 cycles for 100
mult then mult then mflo: 1953 cycles for 100
mult then mtlo then mflo: 655 cycles for 100
loads, 100 turns of the load and a nop:
RAM KSEG0 800298F0 lw: 971 cycles for 100
RAM KSEG1 A00298F0 lw: 965 cycles for 100
scratchpad 1F800100 lw: 563 cycles for 100
BIOS BFC00100 lw: 2953 cycles for 100
BIOS BFC00100 lh: 1756 cycles for 100
BIOS BFC00100 lb: 1153 cycles for 100
EXP1 1F000084 lb: 1153 cycles for 100
EXP2 1F802000 lb: 1553 cycles for 100
EXP3 1FA00000 lh: 1053 cycles for 100
EXP3 1FA00000 lb: 1053 cycles for 100
I_STAT 1F801070 lw: 757 cycles for 100
DPCR 1F8010F0 lw: 757 cycles for 100
timer 0 1F801100 lw: 757 cycles for 100
JOY_STAT 1F801044 lh: 757 cycles for 100
CDROM status 1F801800 lb: 1259 cycles for 100
GPUSTAT 1F801814 lw: 757 cycles for 100
MDEC status 1F801824 lw: 762 cycles for 100
SPUSTAT 1F801DAE lh: 2253 cycles for 100
SPU word 1F801DAC lw: 4253 cycles for 100
cache control FFFE0130 lw: 557 cycles for 100
RAM lw, used at once: 971 cycles for 100
RAM lw, used after 1 nop: 1268 cycles for 100
RAM lw, used after 2 nops: 1363 cycles for 100
RAM lw, used after 3 nops: 1367 cycles for 100
RAM lw then lw: 1464 cycles for 100
BIOS lw, used at once: 2945 cycles for 100
BIOS lw, used after 3 nops: 3330 cycles for 100
stores, 100 turns of n stores:
RAM, 1 sw: 456 cycles for 100
RAM, 2 sw: 568 cycles for 100
RAM, 3 sw: 688 cycles for 100
RAM, 4 sw: 904 cycles for 100
RAM, 5 sw: 1117 cycles for 100
RAM, 6 sw: 1328 cycles for 100
RAM, 7 sw: 1519 cycles for 100
RAM, 8 sw: 1736 cycles for 100
RAM, 4 sw then lw: 2114 cycles for 100
RAM, sw then lw: 1474 cycles for 100
scratchpad, 1 sw: 427 cycles for 100
scratchpad, 8 sw: 1151 cycles for 100
I_MASK, 1 sw: 430 cycles for 100
I_MASK, 4 sw: 852 cycles for 100
I_MASK, sw then lw: 842 cycles for 100
code from uncached RAM (KSEG1):
nop loop: 3110 cycles for 100
nop, 20 nops loop: 15302 cycles for 100
RAM lw loop: 3521 cycles for 100
Done.