===== 06 TIM CPU MULT DIV TIME | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 80017636 cpu/mult div timing (timer 2, system clock) nop 00000000 00000000: 558 cycles for 100 nop, 20 nops 00000000 00000000: 2582 cycles for 100 mult 00000000 00000003: 1154 cycles for 100 multu 00000000 00000003: 1154 cycles for 100 mult rt 00000003 00000000: 1154 cycles for 100 mult 00000001 00000003: 1157 cycles for 100 multu 00000001 00000003: 1153 cycles for 100 mult rt 00000003 00000001: 1153 cycles for 100 mult 000007FF 00000003: 1153 cycles for 100 multu 000007FF 00000003: 1153 cycles for 100 mult rt 00000003 000007FF: 1153 cycles for 100 mult 00000800 00000003: 1453 cycles for 100 multu 00000800 00000003: 1453 cycles for 100 mult rt 00000003 00000800: 1153 cycles for 100 mult 000FFFFF 00000003: 1453 cycles for 100 multu 000FFFFF 00000003: 1453 cycles for 100 mult rt 00000003 000FFFFF: 1153 cycles for 100 mult 00100000 00000003: 1853 cycles for 100 multu 00100000 00000003: 1853 cycles for 100 mult rt 00000003 00100000: 1153 cycles for 100 mult 7FFFFFFF 00000003: 1853 cycles for 100 multu 7FFFFFFF 00000003: 1856 cycles for 100 mult rt 00000003 7FFFFFFF: 1153 cycles for 100 mult FFFFFFFF 00000003: 1153 cycles for 100 multu FFFFFFFF 00000003: 1853 cycles for 100 mult rt 00000003 FFFFFFFF: 1153 cycles for 100 mult 80000000 00000003: 1853 cycles for 100 multu 80000000 00000003: 1853 cycles for 100 mult rt 00000003 80000000: 1154 cycles for 100 div 12345678 00000003: 4154 cycles for 100 divu 12345678 00000003: 4153 cycles for 100 div by 0 12345678 00000000: 4157 cycles for 100 mult, 20 nops 7FFFFFFF 00000003: 2578 cycles for 100 div, 20 nops 12345678 00000003: 4162 cycles for 100 mult 00100000 00000003 then n nops then mflo: mult, 0 nops, mflo: 1859 cycles for 100 mult, 1 nops, mflo: 1854 cycles for 100 mult, 2 nops, mflo: 1854 cycles for 100 mult, 3 nops, mflo: 1849 cycles for 100 mult, 4 nops, mflo: 1847 cycles for 100 mult, 5 nops, mflo: 1852 cycles for 100 mult, 6 nops, mflo: 1853 cycles for 100 mult, 7 nops, mflo: 1857 cycles for 100 mult, 8 nops, mflo: 1852 cycles for 100 mult, 9 nops, mflo: 1854 cycles for 100 mult, 10 nops, mflo: 1862 cycles for 100 mult, 11 nops, mflo: 1856 cycles for 100 mult, 12 nops, mflo: 1762 cycles for 100 mult, 13 nops, mflo: 1875 cycles for 100 mult, 14 nops, mflo: 1970 cycles for 100 div, 5 nops, mflo: 4153 cycles for 100 div, 10 nops, mflo: 4147 cycles for 100 div, 30 nops, mflo: 4176 cycles for 100 div, 33 nops, mflo: 4192 cycles for 100 div, 34 nops, mflo: 4187 cycles for 100 div, 35 nops, mflo: 4092 cycles for 100 div, 36 nops, mflo: 4198 cycles for 100 div, 37 nops, mflo: 4293 cycles for 100 what waits for a busy multiply (rs 00100000): mult then mfhi: 1848 cycles for 100 mult, no read: 457 cycles for 100 div, no read: 450 cycles for 100 mult then mtlo: 551 cycles for 100 mult then mthi: 551 cycles for 100 mult then mult then mflo: 1948 cycles for 100 mult then mtlo then mflo: 648 cycles for 100 loads, 100 turns of the load and a nop: RAM KSEG0 8002CE28 lw: 969 cycles for 100 RAM KSEG1 A002CE28 lw: 948 cycles for 100 scratchpad 1F800100 lw: 533 cycles for 100 BIOS BFC00100 lw: 2936 cycles for 100 BIOS BFC00100 lh: 1748 cycles for 100 BIOS BFC00100 lb: 1143 cycles for 100 EXP1 1F000084 lb: 1124 cycles for 100 EXP2 1F802000 lb: 1528 cycles for 100 EXP3 1FA00000 lh: 1030 cycles for 100 EXP3 1FA00000 lb: 1024 cycles for 100 I_STAT 1F801070 lw: 752 cycles for 100 DPCR 1F8010F0 lw: 736 cycles for 100 timer 0 1F801100 lw: 736 cycles for 100 JOY_STAT 1F801044 lh: 727 cycles for 100 CDROM status 1F801800 lb: 1224 cycles for 100 GPUSTAT 1F801814 lw: 733 cycles for 100 MDEC status 1F801824 lw: 733 cycles for 100 SPUSTAT 1F801DAE lh: 2224 cycles for 100 SPU word 1F801DAC lw: 4230 cycles for 100 cache control FFFE0130 lw: 533 cycles for 100 RAM lw, used at once: 955 cycles for 100 RAM lw, used after 1 nop: 1267 cycles for 100 RAM lw, used after 2 nops: 1360 cycles for 100 RAM lw, used after 3 nops: 1372 cycles for 100 RAM lw then lw: 1470 cycles for 100 BIOS lw, used at once: 2931 cycles for 100 BIOS lw, used after 3 nops: 3327 cycles for 100 stores, 100 turns of n stores: RAM, 1 sw: 460 cycles for 100 RAM, 2 sw: 579 cycles for 100 RAM, 3 sw: 687 cycles for 100 RAM, 4 sw: 905 cycles for 100 RAM, 5 sw: 1108 cycles for 100 RAM, 6 sw: 1333 cycles for 100 RAM, 7 sw: 1536 cycles for 100 RAM, 8 sw: 1746 cycles for 100 RAM, 4 sw then lw: 2115 cycles for 100 RAM, sw then lw: 1477 cycles for 100 scratchpad, 1 sw: 456 cycles for 100 scratchpad, 8 sw: 1163 cycles for 100 I_MASK, 1 sw: 447 cycles for 100 I_MASK, 4 sw: 855 cycles for 100 I_MASK, sw then lw: 849 cycles for 100 a store, n instructions, then a load of its word: RAM sw, 1 nop, lw: 1480 cycles for 100 RAM sw, 2 nops, lw: 1474 cycles for 100 RAM sw, 3 nops, lw: 1474 cycles for 100 RAM sw, 4 nops, lw: 1483 cycles for 100 RAM sw, 6 nops, lw: 1570 cycles for 100 RAM sw, lw of another word: 1467 cycles for 100 RAM 4 sw, lw of another word: 2114 cycles for 100 chain-looping's loop: 1666 cycles for 100 RAM lw, used after 4 nops: 1367 cycles for 100 IO and BIOS loads used after the delay slot: I_STAT lw, used at once: 746 cycles for 100 I_STAT lw, used after 1 nop: 1053 cycles for 100 I_STAT lw, used after 2 nops: 1149 cycles for 100 I_STAT lw then lw: 1154 cycles for 100 BIOS lw, used after 1 nop: 3240 cycles for 100 BIOS lw, used after 2 nops: 3327 cycles for 100 BIOS lw then lw: 5433 cycles for 100 stores to other devices, each writing back what is there: GP0 NOP, 1 sw: 447 cycles for 100 GP0 NOP, 4 sw: 851 cycles for 100 CDROM index, 1 sb: 637 cycles for 100 CDROM index, 4 sb: 2433 cycles for 100 SPU main volume, 1 sh: 828 cycles for 100 SPU main volume, 4 sh: 3212 cycles for 100 scratchpad, 4 sw: 753 cycles for 100 RAM, 1 sh: 459 cycles for 100 RAM, 4 sh: 895 cycles for 100 RAM, 4 sb: 902 cycles for 100 card 5, the store-then-load curve with baselines: RAM sw, 5 nops, lw: 1493 cycles for 100 RAM sw, 7 nops, lw: 1666 cycles for 100 RAM sw, 8 nops, lw: 1786 cycles for 100 RAM 5 nops, lw (no store): 1262 cycles for 100 RAM 7 nops, lw (no store): 1460 cycles for 100 RAM 9 nops, lw (no store): 1670 cycles for 100 chain-looping's loop, the sw a nop: 1465 cycles for 100 I_STAT lw, used after 3 nops: 1149 cycles for 100 I_STAT lw, used after 4 nops: 1155 cycles for 100 SPU word lw then lw: 8254 cycles for 100 mthi and mtlo after a busy multiply (rs 00100000): mult, mthi, mfhi: 655 cycles for 100 mult, mthi, mflo: 652 cycles for 100 mult, mtlo, mfhi: 654 cycles for 100 code from uncached RAM (KSEG1): nop loop: 3110 cycles for 100 nop, 20 nops loop: 15302 cycles for 100 RAM lw loop: 3519 cycles for 100 Done.