===== 06 TIM CPU MULT DIV TIME | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 800175EE cpu/mult div timing (timer 2, system clock) nop 00000000 00000000: 545 cycles for 100 nop, 20 nops 00000000 00000000: 2570 cycles for 100 mult 00000000 00000003: 1145 cycles for 100 multu 00000000 00000003: 1145 cycles for 100 mult rt 00000003 00000000: 1145 cycles for 100 mult 00000001 00000003: 1145 cycles for 100 multu 00000001 00000003: 1145 cycles for 100 mult rt 00000003 00000001: 1145 cycles for 100 mult 000007FF 00000003: 1145 cycles for 100 multu 000007FF 00000003: 1149 cycles for 100 mult rt 00000003 000007FF: 1145 cycles for 100 mult 00000800 00000003: 1445 cycles for 100 multu 00000800 00000003: 1450 cycles for 100 mult rt 00000003 00000800: 1145 cycles for 100 mult 000FFFFF 00000003: 1445 cycles for 100 multu 000FFFFF 00000003: 1445 cycles for 100 mult rt 00000003 000FFFFF: 1149 cycles for 100 mult 00100000 00000003: 1845 cycles for 100 multu 00100000 00000003: 1845 cycles for 100 mult rt 00000003 00100000: 1145 cycles for 100 mult 7FFFFFFF 00000003: 1845 cycles for 100 multu 7FFFFFFF 00000003: 1845 cycles for 100 mult rt 00000003 7FFFFFFF: 1145 cycles for 100 mult FFFFFFFF 00000003: 1145 cycles for 100 multu FFFFFFFF 00000003: 1848 cycles for 100 mult rt 00000003 FFFFFFFF: 1145 cycles for 100 mult 80000000 00000003: 1845 cycles for 100 multu 80000000 00000003: 1845 cycles for 100 mult rt 00000003 80000000: 1145 cycles for 100 div 12345678 00000003: 4145 cycles for 100 divu 12345678 00000003: 4150 cycles for 100 div by 0 12345678 00000000: 4145 cycles for 100 mult, 20 nops 7FFFFFFF 00000003: 2570 cycles for 100 div, 20 nops 12345678 00000003: 4159 cycles for 100 mult 00100000 00000003 then n nops then mflo: mult, 0 nops, mflo: 1845 cycles for 100 mult, 1 nops, mflo: 1846 cycles for 100 mult, 2 nops, mflo: 1848 cycles for 100 mult, 3 nops, mflo: 1854 cycles for 100 mult, 4 nops, mflo: 1851 cycles for 100 mult, 5 nops, mflo: 1852 cycles for 100 mult, 6 nops, mflo: 1857 cycles for 100 mult, 7 nops, mflo: 1856 cycles for 100 mult, 8 nops, mflo: 1856 cycles for 100 mult, 9 nops, mflo: 1859 cycles for 100 mult, 10 nops, mflo: 1854 cycles for 100 mult, 11 nops, mflo: 1858 cycles for 100 mult, 12 nops, mflo: 1771 cycles for 100 mult, 13 nops, mflo: 1867 cycles for 100 mult, 14 nops, mflo: 1974 cycles for 100 div, 5 nops, mflo: 4147 cycles for 100 div, 10 nops, mflo: 4151 cycles for 100 div, 30 nops, mflo: 4179 cycles for 100 div, 33 nops, mflo: 4188 cycles for 100 div, 34 nops, mflo: 4191 cycles for 100 div, 35 nops, mflo: 4086 cycles for 100 div, 36 nops, mflo: 4194 cycles for 100 div, 37 nops, mflo: 4298 cycles for 100 what waits for a busy multiply (rs 00100000): mult then mfhi: 1842 cycles for 100 mult, no read: 441 cycles for 100 div, no read: 451 cycles for 100 mult then mtlo: 552 cycles for 100 mult then mthi: 552 cycles for 100 mult then mult then mflo: 1945 cycles for 100 mult then mtlo then mflo: 653 cycles for 100 loads, 100 turns of the load and a nop: RAM KSEG0 8002CD90 lw: 967 cycles for 100 RAM KSEG1 A002CD90 lw: 943 cycles for 100 scratchpad 1F800100 lw: 531 cycles for 100 BIOS BFC00100 lw: 2926 cycles for 100 BIOS BFC00100 lh: 1745 cycles for 100 BIOS BFC00100 lb: 1145 cycles for 100 EXP1 1F000084 lb: 1120 cycles for 100 EXP2 1F802000 lb: 1520 cycles for 100 EXP3 1FA00000 lh: 1041 cycles for 100 EXP3 1FA00000 lb: 1045 cycles for 100 I_STAT 1F801070 lw: 748 cycles for 100 DPCR 1F8010F0 lw: 731 cycles for 100 timer 0 1F801100 lw: 731 cycles for 100 JOY_STAT 1F801044 lh: 725 cycles for 100 CDROM status 1F801800 lb: 1220 cycles for 100 GPUSTAT 1F801814 lw: 731 cycles for 100 MDEC status 1F801824 lw: 731 cycles for 100 SPUSTAT 1F801DAE lh: 2220 cycles for 100 SPU word 1F801DAC lw: 4226 cycles for 100 cache control FFFE0130 lw: 531 cycles for 100 RAM lw, used at once: 961 cycles for 100 RAM lw, used after 1 nop: 1269 cycles for 100 RAM lw, used after 2 nops: 1356 cycles for 100 RAM lw, used after 3 nops: 1358 cycles for 100 RAM lw then lw: 1462 cycles for 100 BIOS lw, used at once: 2937 cycles for 100 BIOS lw, used after 3 nops: 3325 cycles for 100 stores, 100 turns of n stores: RAM, 1 sw: 454 cycles for 100 RAM, 2 sw: 570 cycles for 100 RAM, 3 sw: 693 cycles for 100 RAM, 4 sw: 893 cycles for 100 RAM, 5 sw: 1114 cycles for 100 RAM, 6 sw: 1327 cycles for 100 RAM, 7 sw: 1523 cycles for 100 RAM, 8 sw: 1747 cycles for 100 RAM, 4 sw then lw: 2120 cycles for 100 RAM, sw then lw: 1479 cycles for 100 scratchpad, 1 sw: 446 cycles for 100 scratchpad, 8 sw: 1156 cycles for 100 I_MASK, 1 sw: 447 cycles for 100 I_MASK, 4 sw: 851 cycles for 100 I_MASK, sw then lw: 852 cycles for 100 a store, n instructions, then a load of its word: RAM sw, 1 nop, lw: 1485 cycles for 100 RAM sw, 2 nops, lw: 1492 cycles for 100 RAM sw, 3 nops, lw: 1487 cycles for 100 RAM sw, 4 nops, lw: 1483 cycles for 100 RAM sw, 6 nops, lw: 1579 cycles for 100 RAM sw, lw of another word: 1474 cycles for 100 RAM 4 sw, lw of another word: 2115 cycles for 100 chain-looping's loop: 1649 cycles for 100 RAM lw, used after 4 nops: 1364 cycles for 100 IO and BIOS loads used after the delay slot: I_STAT lw, used at once: 755 cycles for 100 I_STAT lw, used after 1 nop: 1039 cycles for 100 I_STAT lw, used after 2 nops: 1147 cycles for 100 I_STAT lw then lw: 1150 cycles for 100 BIOS lw, used after 1 nop: 3239 cycles for 100 BIOS lw, used after 2 nops: 3325 cycles for 100 BIOS lw then lw: 5423 cycles for 100 stores to other devices, each writing back what is there: GP0 NOP, 1 sw: 447 cycles for 100 GP0 NOP, 4 sw: 851 cycles for 100 CDROM index, 1 sb: 626 cycles for 100 CDROM index, 4 sb: 2433 cycles for 100 SPU main volume, 1 sh: 806 cycles for 100 SPU main volume, 4 sh: 3220 cycles for 100 scratchpad, 4 sw: 753 cycles for 100 RAM, 1 sh: 436 cycles for 100 RAM, 4 sh: 892 cycles for 100 RAM, 4 sb: 872 cycles for 100 card 5, the store-then-load curve with baselines: RAM sw, 5 nops, lw: 1489 cycles for 100 RAM sw, 7 nops, lw: 1658 cycles for 100 RAM sw, 8 nops, lw: 1785 cycles for 100 RAM 5 nops, lw (no store): 1254 cycles for 100 RAM 7 nops, lw (no store): 1468 cycles for 100 RAM 9 nops, lw (no store): 1667 cycles for 100 chain-looping's loop, the sw a nop: 1480 cycles for 100 I_STAT lw, used after 3 nops: 1154 cycles for 100 I_STAT lw, used after 4 nops: 1144 cycles for 100 SPU word lw then lw: 8247 cycles for 100 mthi and mtlo after a busy multiply (rs 00100000): mult, mthi, mfhi: 653 cycles for 100 mult, mthi, mflo: 651 cycles for 100 mult, mtlo, mfhi: 653 cycles for 100 code from uncached RAM (KSEG1): nop loop: 3110 cycles for 100 nop, 20 nops loop: 15300 cycles for 100 RAM lw loop: 3523 cycles for 100 Done.