===== 05 DLY CPU DELAYS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 8001554A

cpu/delays
lw 2 over 1: in the delay 00000001, after 00000002
lw 2 then li 5 in the delay: 00000005
lw 2 then lw 3: 00000001 00000003 00000003
mfc0 SR over 1: in the delay 00000001, after 40000401
mtc0 BDA then mfc0 at once: 12345678, after clearing 00000000
mtc2 00050006 then mfc2 over 1: 00000001 7FFF8000 7FFF8000
jal: ra - jal 8
beq in a beq's delay slot: 00001001 (1 and 16 from the first target, 256 and 4096 from the second)
jalr in a beq's delay slot: 00001101, ra - first target 4
jr in a jr's delay slot: 00001101
bne not taken in a beq's delay slot: 00000011
beq in a not taken bne's delay slot: 00001101
bltzal not taken in a beq's delay slot: ra - first target 4
GTE moves, old value 00010002, new 00030004:
mtc2 then mfc2 at once: cold 00010002, cached 00010002, four later 00030004
mtc2, 1 nop, mfc2: cold 00030004, cached 00010002, four later 00030004
mtc2, 2 nops, mfc2: cold 00030004, cached 00030004, four later 00030004
mtc2, 3 nops, mfc2: cold 00030004, cached 00030004, four later 00030004
lwc2 then mfc2 at once: cold 00010002, cached 00010002, four later 00030004
lwc2, 1 nop, mfc2: cold 00010002, cached 00010002, four later 00030004
lwc2, 2 nops, mfc2: cold 00030004, cached 00030004, four later 00030004
lwc2, 3 nops, mfc2: cold 00030004, cached 00030004, four later 00030004
ctc2 then cfc2 at once: cold 00010002, cached 00010002, four later 00030004
ctc2, 1 nop, cfc2: cold 00030004, cached 00010002, four later 00030004
ctc2, 2 nops, cfc2: cold 00030004, cached 00030004, four later 00030004
mtc2 IR1 then SQR at once (MAC1): cold 00000004, cached 00000004, four later 00000010
mtc2 IR1, 1 nop, SQR: cold 00000010, cached 00000004, four later 00000010
mtc2 IR1, 2 nops, SQR: cold 00000010, cached 00000010, four later 00000100
mtc2 IR1, 3 nops, SQR: cold 00000010, cached 00000010, four later 00000100
lwc2 IR1 then SQR at once: cold 00000004, cached 00000004, four later 00000010
lwc2 IR1, 1 nop, SQR: cold 00000004, cached 00000004, four later 00000010
mtc2 then swc2 at once: cold 00010002, cached 00010002, four later 00030004
mtc2, 1 nop, swc2: cold 00010002, cached 00010002, four later 00030004
mtc2, 2 nops, swc2: cold 00030004, cached 00030004, four later 00030004
mtc2 IR1, lw, SQR: cold 00000010, cached 00000004, four later 00000010
mtc2 IR1, mtc2 VXY0, SQR: cold 00000010, cached 00000004, four later 00000010
lwc2 IR1, lwc2 VXY0, SQR: cold 00000010, cached 00000010, four later 00000100
lwc2 IR1, 2 nops, SQR: cold 00000010, cached 00000010, four later 00000100
mtc2 VZ2 then RTPT at once (MAC3): cold 00000004, cached 00000004, four later 00000004
mtc2 VZ2, 1 nop, RTPT: cold 00000004, cached 00000004, four later 00000004
lwc2 VZ2 then RTPT at once: cold 00000004, cached 00000004, four later 00000004
lwc2 VZ2, 1 nop, RTPT: cold 00000004, cached 00000004, four later 00000004
lwc2 VZ2, lwc2 VXY0, RTPT: cold 00000004, cached 00000004, four later 00000004
ctc2 TRZ then RTPT at once: cold 00030008, cached 00030008, four later 00030008
ctc2 TRZ, 1 nop, RTPT: cold 00030008, cached 00030008, four later 00030008
ctc2 TRZ, 2 nops, RTPT: cold 00030008, cached 00030008, four later 00030008
mtc2 IR2 then SQR at once (MAC2): cold 00000004, cached 00000004, four later 00000010
mtc2 IR3 then SQR at once (MAC3): cold 00000010, cached 00000010, four later 00000100
mtc2 IR3, 1 nop, SQR (MAC3): cold 00000010, cached 00000010, four later 00000100
mtc2 RGBC then NCCS at once (MAC1): cold 00000040, cached 00000040, four later 00000040
lwc2 RGBC then NCCS at once: cold 00000040, cached 00000040, four later 00000040
mtc2 RGBC, 1 nop, NCCS: cold 00000040, cached 00000040, four later 00000040
mtc2 VZ0 then RTPS at once (MAC3): cold 00000004, cached 00000004, four later 00000004
lwc2 VZ0 then RTPS at once: cold 00000004, cached 00000004, four later 00000004
mtc2 VZ0 then MVMVA at once (MAC3): cold 00000004, cached 00000004, four later 00000004
lwc2 VZ0 then MVMVA at once: cold 00000004, cached 00000004, four later 00000004
mtc2 IR1 then INTPL at once (MAC1): cold 00000002, cached 00000002, four later 00000002
mtc2 IR3 then INTPL at once (MAC3): cold 00000004, cached 00000004, four later 00000004
mtc2 VXY0 then RTPS at once (MAC1 = VX0): cold 00000004, cached 00000004, four later 00000004
mtc2 VXY0 then RTPS at once (MAC2 = VY0): cold 00000003, cached 00000003, four later 00000003
ctc2 TRX then RTPS at once (MAC1 = TRX + VX0): cold 00030008, cached 00030008, four later 00030008
mtc2 VZ0 then RTPT at once (SZ1): cold 00000004, cached 00000004, four later 00000004
lwc2 VZ0 then RTPT at once (SZ1): cold 00000004, cached 00000004, four later 00000004
mtc2 VZ1 then RTPT at once (SZ2): cold 00000004, cached 00000004, four later 00000004
mtc2 LZCS then mfc2 LZCR at once: cold 0000000F, cached 0000000F, four later 0000000E
mtc2 LZCS, 1 nop, mfc2 LZCR: cold 0000000F, cached 0000000F, four later 0000000E
mtc2 LZCS, 2 nops, mfc2 LZCR: cold 0000000E, cached 0000000E, four later 0000000E
mtc2 IRGB then mfc2 IR1 at once: cold 00000100, cached 00000100, four later 00000200
mtc2 IRGB, 1 nop, mfc2 IR1: cold 00000200, cached 00000100, four later 00000200
mtc2 IRGB, 2 nops, mfc2 IR1: cold 00000100, cached 00000100, four later 00000200
mtc2 SXYP then mfc2 SXY2 at once: cold 00010002, cached 00010002, four later 00030004
mtc2 SXYP, 1 nop, mfc2 SXY2: cold 00010002, cached 00010002, four later 00030004
mtc2 SXYP, 2 nops, mfc2 SXY2: cold 00030004, cached 00030004, four later 00030004
Done.