===== 11 TMR TIMERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A timers test Detected NTSC system. Forced NTSC system. Timer0, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer0, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer0, clock: System clock, frame delay: 106456, 107368, 107325, 107349, 107335, 107363, 107359, 107329, 107341, 107335, Timer0, clock: Dot clock, 1000 cycles delay: 200, 200, 201, 200, 200, 201, 200, 200, 199, 200, Timer0, clock: Dot clock, 5000 cycles delay: 991, 992, 992, 991, 992, 992, 991, 992, 992, 991, Timer0, clock: Dot clock, frame delay: 111937, 112029, 112035, 112027, 112036, 112036, 112031, 112034, 112032, 112031, Timer1, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer1, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer1, clock: System clock, frame delay: 106859, 107349, 107343, 107335, 107371, 107320, 107357, 107344, 107335, 107371, Timer1, clock: Hblank, 1000 cycles delay: 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, Timer1, clock: Hblank, 5000 cycles delay: 2, 2, 2, 2, 3, 2, 2, 3, 2, 2, Timer1, clock: Hblank, frame delay: 263, 263, 263, 263, 263, 263, 263, 263, 263, 263, Timer2, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer2, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer2, clock: System clock, frame delay: 106836, 107364, 107341, 107328, 107389, 107313, 107363, 107333, 107339, 107379, Timer2, clock: System clock/8, 1000 cycles delay: 126, 127, 126, 126, 127, 126, 126, 127, 126, 127, Timer2, clock: System clock/8, 5000 cycles delay: 626, 626, 627, 626, 627, 626, 626, 627, 626, 626, Timer2, clock: System clock/8, frame delay: 70700, 70761, 70763, 70762, 70760, 70761, 70761, 70763, 70764, 70759, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs) 0 = Pause counter during Hblanks 304, 426, 548, 604, 604, 604, 604, 619, 741, 863, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 41, 163, 285, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs) 0 = Pause counter during Hblanks 290, 327, 327, 327, 327, 361, 483, 605, 727, 849, 1 = Reset counter to 0 at Hblanks 254, 85, 207, 329, 451, 573, 695, 817, 939, 1061, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 13, 135, 257, 379, 3 = Pause until Hblank occurs once, then switch to Free Run 22, 144, 266, 388, 510, 632, 754, 876, 998, 1120, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs) 0 = Pause counter during Hblanks 294, 416, 538, 660, 782, 904, 972, 972, 972, 972, 1 = Reset counter to 0 at Hblanks 240, 15, 137, 259, 381, 503, 625, 747, 869, 991, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 55, 177, 299, 421, 3 = Pause until Hblank occurs once, then switch to Free Run 193, 315, 437, 559, 681, 803, 925, 1047, 1169, 1291, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs) 0 = Pause counter during Hblanks 68, 190, 312, 434, 556, 678, 800, 922, 1044, 1166, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 11, 133, 255, 377, 499, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 61, 183, 305, 427, 549, 671, 793, 915, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs) 0 = Pause counter during Hblanks 122, 244, 366, 488, 610, 732, 854, 976, 1098, 1220, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs) 0 = Pause counter during Hblanks 46, 49, 49, 49, 49, 57, 76, 95, 115, 134, 1 = Reset counter to 0 at Hblanks 38, 58, 77, 96, 116, 135, 154, 174, 193, 212, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 37, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs) 0 = Pause counter during Hblanks 59, 84, 108, 132, 156, 180, 204, 229, 253, 277, 1 = Reset counter to 0 at Hblanks 6, 31, 55, 79, 103, 127, 151, 176, 200, 224, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 47, 72, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs) 0 = Pause counter during Hblanks 66, 94, 121, 149, 177, 204, 232, 234, 234, 234, 1 = Reset counter to 0 at Hblanks 54, 82, 110, 137, 165, 193, 220, 248, 276, 303, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 2, 29, 57, 84, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 24, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs) 0 = Pause counter during Hblanks 24, 24, 24, 34, 73, 112, 151, 189, 228, 267, 1 = Reset counter to 0 at Hblanks 76, 114, 153, 31, 69, 108, 147, 185, 224, 263, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 36, 74, 113, 151, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs) 0 = Pause counter during Hblanks 119, 167, 215, 264, 312, 360, 409, 457, 505, 544, 1 = Reset counter to 0 at Hblanks 94, 143, 191, 35, 84, 132, 180, 229, 277, 325, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 44, 92, 140, 189, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer1 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Pause counter during Vblanks 285, 407, 529, 651, 773, 895, 1017, 1139, 1261, 1383, 1 = Reset counter to 0 at Vblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Vblanks and pause outside of Vblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Vblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer1 sync modes (clock source = Hblank, 100 delay cycles, not resetted between runs) 0 = Pause counter during Vblanks 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 = Reset counter to 0 at Vblanks 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2 = Reset counter to 0 at Vblanks and pause outside of Vblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Vblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 = Free Run 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Free Run 254, 376, 498, 620, 742, 864, 986, 1108, 1230, 1352, 3 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 = Free Run 239, 361, 483, 605, 727, 849, 971, 1093, 1215, 1337, 2 = Free Run 239, 361, 483, 605, 727, 849, 971, 1093, 1215, 1337, 3 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Check when Timer2 counter (System clock) is reset when reaching target (= 10). counter == 0, 1665 ticks counter == 1, 835 ticks counter == 2, 831 ticks counter == 3, 834 ticks counter == 4, 836 ticks counter == 5, 831 ticks counter == 6, 834 ticks counter == 7, 835 ticks counter == 8, 831 ticks counter == 9, 834 ticks counter == 10, 834 ticks <<<< This value should be non-zero counter == 11, 0 ticks Reached target: 1 (ok) Reached 0xFFFF: 0 (ok) Counter reset AFTER reaching target: 1 (ok) Target + 1 not reached: 1 (ok) Check if write to mode register acknowledges the targetReached flag Write 0x0000 to Timer0.mode, read 0x0400 Write 0xffff to Timer0.mode, read 0x07ff Read mode after waiting for targetReached: 0x1c08 Read again: 0x0408 Write mode after waiting for targetReached and then read: 0x1c08 Read again: 0x0408 Done.