===== 05 DSP DMA SPU TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA4 to and from sound RAM at 1000h: clocks from the CHCR write to bit 24 clear (polls meanwhile), three times each; MADR, BCR, CHCR after. SPU delay was 220931E1, 220931E1 here.
Write SyncMode 1, 16 words x 1: 202 (0) 192 (0) 191 (0) | MADR start64, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 2: 1492 (89) 1470 (88) 1479 (89) | MADR start128, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 4: 3842 (250) 3814 (249) 3833 (250) | MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 8: 8545 (572) 8520 (571) 8537 (572) | MADR start512, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16: 17789 (1202) 17772 (1202) 17772 (1202) | MADR start1024, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 64: 73072 (4969) 73068 (4970) 73068 (4970) | MADR start4096, BCR 00000010, CHCR 00000201
Write SyncMode 1, 1 word x 64: 4080 (265) 4060 (264) 4071 (265) | MADR start256, BCR 00000001, CHCR 00000201
Write SyncMode 1, 2 words x 32: 4885 (331) 4864 (331) 4855 (330) | MADR start256, BCR 00000002, CHCR 00000201
Write SyncMode 1, 4 words x 16: 4490 (299) 4470 (299) 4477 (299) | MADR start256, BCR 00000004, CHCR 00000201
Write SyncMode 1, 8 words x 8: 4280 (284) 4271 (284) 4472 (299) | MADR start256, BCR 00000008, CHCR 00000201
Read SyncMode 1, 16 words x 1: 203 (0) 191 (0) 200 (1) | MADR start64, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 4: 3897 (255) 3894 (256) 3879 (255) | MADR start256, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16: 17790 (1207) 17783 (1208) 17780 (1208) | MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 64: 73102 (5001) 73102 (5002) 73076 (5000) | MADR start4096, BCR 00000010, CHCR 00000200
Read SyncMode 1, 4 words x 16: 4796 (324) 4777 (324) 4780 (324) | MADR start256, BCR 00000004, CHCR 00000200
Write SyncMode 0, 16 words: 206 (0) 190 (0) 192 (0) | MADR start0, BCR 00000010, CHCR 00000001
Write SyncMode 0, 64 words: 590 (0) 577 (0) 572 (0) | MADR start0, BCR 00000040, CHCR 00000001
Write SyncMode 0, 256 words: 2125 (0) 2112 (0) 2114 (0) | MADR start0, BCR 00000100, CHCR 00000001
Write SyncMode 0 bit 28, 64 words: 589 (0) 572 (0) 572 (0) | MADR start0, BCR 00000040, CHCR 00000001
Read SyncMode 0, 64 words: 629 (2) 624 (3) 635 (4) | MADR start0, BCR 00000040, CHCR 00000000
Read SyncMode 0 bit 28, 64 words: 605 (0) 584 (0) 589 (0) | MADR start0, BCR 00000040, CHCR 00000000
Write SyncMode 1 bit 28, 16 words x 4: 3845 (250) 3828 (250) 3833 (250) | MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16, SPU delay 220931F1: 17766 (1200) 17755 (1200) 17755 (1200) | MADR start1024, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 16, SPU delay 220931F1: 17803 (1209) 17794 (1209) 17791 (1209) | MADR start1024, BCR 00000010, CHCR 00000200
Write SyncMode 1, 16 words x 16, SPU delay 22093141: 17524 (1180) 17675 (1194) 17675 (1194) | MADR start1024, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 16, delay 200931E1: 16879 (1215) 16872 (1217) 16854 (1214) | MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16, delay 220931E1: 17799 (1208) 17783 (1208) 17780 (1208) | MADR start1024, BCR 00000010, CHCR 00000200
64 words written then read back, SyncMode 1: 56 of 64 match
64 words written then read back, SyncMode 0: 16 of 64 match
Done.