===== 11 TMR TIMERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A timers test Detected NTSC system. Forced NTSC system. Timer0, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer0, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer0, clock: System clock, frame delay: 106459, 107363, 107335, 107352, 107339, 107326, 107354, 107343, 107349, 107339, Timer0, clock: Dot clock, 1000 cycles delay: 200, 200, 201, 200, 201, 200, 200, 200, 199, 200, Timer0, clock: Dot clock, 5000 cycles delay: 991, 992, 992, 991, 992, 992, 991, 991, 992, 992, Timer0, clock: Dot clock, frame delay: 111936, 112032, 112033, 112032, 112035, 112028, 112035, 112032, 112033, 112035, Timer1, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer1, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer1, clock: System clock, frame delay: 106867, 107340, 107347, 107347, 107334, 107359, 107340, 107369, 107325, 107333, Timer1, clock: Hblank, 1000 cycles delay: 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, Timer1, clock: Hblank, 5000 cycles delay: 2, 2, 3, 2, 2, 2, 2, 3, 2, 2, Timer1, clock: Hblank, frame delay: 263, 263, 263, 263, 263, 263, 263, 263, 263, 263, Timer2, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer2, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer2, clock: System clock, frame delay: 106861, 107329, 107341, 107335, 107363, 107359, 107329, 107358, 107317, 107364, Timer2, clock: System clock/8, 1000 cycles delay: 126, 126, 127, 126, 126, 127, 126, 127, 126, 126, Timer2, clock: System clock/8, 5000 cycles delay: 627, 626, 626, 627, 626, 627, 626, 626, 627, 626, Timer2, clock: System clock/8, frame delay: 70704, 70762, 70760, 70761, 70763, 70761, 70762, 70761, 70760, 70764, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs) 0 = Pause counter during Hblanks 306, 428, 550, 562, 562, 562, 562, 621, 743, 865, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 114, 236, 358, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs) 0 = Pause counter during Hblanks 290, 412, 450, 450, 450, 450, 483, 605, 727, 849, 1 = Reset counter to 0 at Hblanks 254, 376, 49, 171, 293, 415, 537, 659, 781, 903, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 52, 174, 296, 418, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 169, 291, 413, 535, 657, 779, 901, 1023, 1145, 1267, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs) 0 = Pause counter during Hblanks 300, 422, 544, 666, 788, 910, 1032, 1154, 1276, 1398, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 72, 194, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs) 0 = Pause counter during Hblanks 65, 187, 309, 431, 553, 675, 797, 919, 1041, 1163, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 28, 150, 272, 394, 516, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 70, 192, 314, 436, 558, 680, 802, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs) 0 = Pause counter during Hblanks 285, 407, 529, 651, 773, 895, 1017, 1139, 1261, 1383, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs) 0 = Pause counter during Hblanks 35, 35, 35, 35, 36, 55, 74, 94, 113, 132, 1 = Reset counter to 0 at Hblanks 38, 57, 77, 96, 115, 135, 154, 173, 193, 212, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs) 0 = Pause counter during Hblanks 59, 83, 107, 131, 156, 180, 204, 228, 245, 245, 1 = Reset counter to 0 at Hblanks 48, 72, 96, 120, 144, 168, 193, 217, 241, 265, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 47, 71, 95, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 5, 29, 53, 77, 102, 126, 150, 174, 198, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs) 0 = Pause counter during Hblanks 67, 86, 86, 86, 86, 101, 129, 156, 184, 211, 1 = Reset counter to 0 at Hblanks 55, 82, 109, 137, 19, 46, 74, 101, 129, 157, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 1, 28, 56, 84, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs) 0 = Pause counter during Hblanks 0, 0, 31, 69, 108, 147, 186, 224, 263, 302, 1 = Reset counter to 0 at Hblanks 67, 106, 144, 183, 222, 260, 299, 338, 376, 415, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 14, 52, 91, 130, 168, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs) 0 = Pause counter during Hblanks 118, 167, 215, 263, 312, 360, 408, 457, 505, 553, 1 = Reset counter to 0 at Hblanks 95, 143, 191, 17, 65, 114, 162, 210, 259, 307, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 32, 81, 129, 177, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer1 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Pause counter during Vblanks 285, 407, 529, 651, 773, 895, 1017, 1139, 1261, 1383, 1 = Reset counter to 0 at Vblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Vblanks and pause outside of Vblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Vblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer1 sync modes (clock source = Hblank, 100 delay cycles, not resetted between runs) 0 = Pause counter during Vblanks 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 = Reset counter to 0 at Vblanks 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2 = Reset counter to 0 at Vblanks and pause outside of Vblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Vblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 = Free Run 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Free Run 254, 376, 498, 620, 742, 864, 986, 1108, 1230, 1352, 3 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 = Free Run 239, 361, 483, 605, 727, 849, 971, 1093, 1215, 1337, 2 = Free Run 239, 361, 483, 605, 727, 849, 971, 1093, 1215, 1337, 3 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Check when Timer2 counter (System clock) is reset when reaching target (= 10). counter == 0, 1665 ticks counter == 1, 834 ticks counter == 2, 831 ticks counter == 3, 834 ticks counter == 4, 837 ticks counter == 5, 831 ticks counter == 6, 834 ticks counter == 7, 835 ticks counter == 8, 831 ticks counter == 9, 834 ticks counter == 10, 834 ticks <<<< This value should be non-zero counter == 11, 0 ticks Reached target: 1 (ok) Reached 0xFFFF: 0 (ok) Counter reset AFTER reaching target: 1 (ok) Target + 1 not reached: 1 (ok) Check if write to mode register acknowledges the targetReached flag Write 0x0000 to Timer0.mode, read 0x0400 Write 0xffff to Timer0.mode, read 0x07ff Read mode after waiting for targetReached: 0x1c08 Read again: 0x0408 Write mode after waiting for targetReached and then read: 0x1c08 Read again: 0x0408 Done.