===== 16 RST MDEC RESET MID | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
15 bit decode, 32 words in (up to 100 while bit 30 clear), 10 read; status 360000DF; reset: status 26000000, reads 8C830000 24843270
Then the 8 bit block with the step tables kept: 16 words, CRC 728FE2ED, status 8204FFFF
00FFFF00 0004FFFF EDEFECC9 00F2FCEF E8FADBD5 00FFE8FE EFECF3B7 00E3FFEB
F5FFFB00 0003FFF2 FCFF0500 001A08FF FF1E280F 00232A05 29403810 0F163232
Control E0000000h: status 80040000
Decode 24 bit signed bit 15 for 5, then reset: status A5840000
Quant load of 1s cut after 10 words by reset, then the block: 16 words, CRC 8B958491
10C09E66 B31D9FDE BC8059AD 4AE06964 A99E6592 51DE547B A06C8597 74A1708B
6173E444 AB0FD39B 46C75290 848753C1 FF2E8D82 6096AB10 70868775 8B608D84
DMA both ways, reset after DMA1 BCR 000D0020 (DMA0 BCR 00040020): status E6030062, later 80040000
  later: CHCR0 01000201 BCR0 00040020 MADR0 00100F28; CHCR1 01000200 BCR1 000D0020 MADR1 00120238
  words DMA1 wrote: 96, CRC of the first 96: 1E01317C
Step stream by CPU after it: 512 words, CRC 01471D2F, status 8604FFFF
Done.