===== 13 XFR SPU TRANSFERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Scratch at 30000h (6000h), filled with EEEEh before each row, read back by DMA
with transfer control 0004h. Halfwords written: A000h, A001h, ...
Transfer address write 6000h reads 6000, after 8 manual 6000, after DMA 6000
Fifo 1DA8h reads A007 A007
4 manual, then 4 more (A008h..) with no new address: A000 A001 A002 A003 A008 A009 A00A A00B EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE
4 manual, then 4 written to the Fifo in Manual Write mode: A000 A001 A002 A003 EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE
40 halfwords into the Fifo (32 deep, spx:741): A000 A001 A002 A003 A004 A005 A006 A007 A008 A009 A00A A00B A00C A00D A00E A00F A010 A011 A012 A013 A014 A015 A016 A017 A018 A019 A01A A01B A01C A01D A01E A01F EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE
Type 0 manual 8: A007 EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE
Type 1 manual 8: A007 EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE
Type 2 manual 8: A000 A001 A002 A003 A004 A005 A006 A007 EEEE EEEE
Type 3 manual 8: A000 A002 A004 A006 EEEE EEEE EEEE EEEE EEEE EEEE
Type 4 manual 8: A003 A007 EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE
Type 5 manual 8: A006 EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE
Type 6 manual 8: A007 EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE
Type 7 manual 8: A007 EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE
Type 3 DMA write of B000h, B001h, ..: B000 B002 B004 EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE
Type 3 DMA read of C000h, C001h, ..: C000 0000 C001 0000 C002 0000 C003 0000 C004 FFFF C005 FFFF EEEE FFFF EEEE 0000 EEEE 0000 EEEE 0000
Type 4 DMA read of C000h, C001h, ..: C000 C000 C000 C000 C001 C001 C001 C001 C002 C002 C002 C002 C003 C003 C003 C003 C004 C004 C004 C004
Type 5 DMA read of C000h, C001h, ..: C000 0000 C000 0000 C000 0000 C000 0000 C001 0000 C001 0000 C001 0000 C001 0000 C002 0000 C002 FFFF
Manual Write of 1, SPUSTAT (bit 11 masked) was 0000, from the SPUCNT write: 744:0010
Manual Write of 4, SPUSTAT (bit 11 masked) was 0000, from the SPUCNT write: 314:0010
Manual Write of 16, SPUSTAT (bit 11 masked) was 0000, from the SPUCNT write: 196:0410 998:0010
1F801014h 200931E1h, DMA read 128 bytes of D000h..:
  FFFF D000 D001 D002 D003 D004 A005 A006 A007 A008 A009 A00A A00B A00C A00D A00E
  A00F EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE
  FFFF EEEE EEEE EEEE EEEE EEEE EEEE EEEE
1F801014h 200931E1h, DMA read 128 bytes of D000h..:
  FFFF D000 D001 D002 D003 D004 A005 A006 A007 A008 A009 A00A A00B A00C A00D A00E
  A00F EEEE FFFF EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE
  FFFF EEEE EEEE EEEE EEEE EEEE EEEE EEEE
Done.