===== 08 RC8 TIMER SYNC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Timer0 sysclock free, cycles between two hblank ticks: 2146 2154 2143 2154 2143 2154 2154 2154
Timer0 sysclock sync 0 (pause in hblank), counted between two ticks: 1614 1614 1613 1613 1613 1614 1614 1614
Timer0 sysclock sync 1 (reset at hblank), value at a tick: 1637 1630 1634 1627 1630 1623 1627 1631
Timer0 sysclock sync 2 (count in hblank only), value at a tick: 25 18 11 15 19 12 16 19
Timer0 dotclock sync 0, dots counted between two ticks: 639 639 639 639 640 639 639 639
Timer0 dotclock sync 1, value at a tick: 647 644 641 644 644 642 643 645
Timer1 sysclock sync 1 (reset at vblank), value at the vblank IRQ: 55425 57884 57876 57880
Timer1 sysclock sync 2 (count in vblank), 20000 cycles after the IRQ: 20165 20113 20094 20121
Timer1 sysclock sync 2, 100000 cycles after the IRQ: 0 0 0 0
Timer1 hblank sync 2, lines 100000 cycles after the IRQ: 0 0 0 0
Timer1 hblank sync 0 (pause in vblank), lines from one IRQ to the next: 239 239 239 239
Timer1 hblank free, lines from one IRQ to the next: 263 263 263 263
Timer1 hblank sync 1, value at the vblank IRQ: 237 237 237 237
Timer0 sysclock sync 3: mode 0407 at once, 0407 5000 cycles on, counter then 3547
Timer0 dotclock sync 3: mode 0507 at once, 0507 5000 cycles on, counter then 1923
Timer1 sysclock sync 3: mode 0407 at once, 0407 5000 cycles after the vblank, counter then 0
Timer1 hblank sync 3: mode 0507 at once, 0507 5000 cycles after the vblank, counter then 240
Timer2 sysclock sync 3: mode 0407 at once, 0407 5000 cycles after the vblank, counter then 0
Timer2 sysclock sync 1: mode 0403 at once, 0403 5000 cycles on, counter then 5146
Timer1 sysclock sync 0: mode 0401 at once, 1C01 5000 cycles after the vblank, counter then 28492
Done.