===== 04 SRT SPU READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 SPU reads at 1F801C00, SPU delay 200931E1: SPU lw, read delay 0: 1465, value FFFFFFFF SPU lw, read delay 1: 1648, value FFFFFFFF SPU lw, read delay 2: 1848, value FFFFFFFF SPU lw, read delay 3: 2048, value FFFFFFFF SPU lw, read delay 4: 2252, value FFFFFFFF SPU lw, read delay 5: 2448, value FFFFFFFF SPU lw, read delay 6: 2653, value FFFFFFFF SPU lw, read delay 7: 2853, value FFFFFFFF SPU lw, read delay 8: 3048, value FFFFFFFF SPU lw, read delay 9: 3252, value FFFFFFFF SPU lw, read delay 10: 3448, value FFFFFFFF SPU lw, read delay 11: 3648, value 00000000 SPU lw, read delay 12: 3848, value 00000000 SPU lw, read delay 13: 4048, value 00000000 SPU lw, read delay 14: 4248, value 00000000 SPU lw, read delay 15: 4457, value 00000000 SPU lhu, read delay 0: 845, value 0000FFFF SPU lhu, read delay 1: 950, value 0000FFFF SPU lhu, read delay 2: 1045, value 0000FFFF SPU lhu, read delay 3: 1147, value 0000FFFF SPU lhu, read delay 4: 1245, value 0000FFFF SPU lhu, read delay 5: 1345, value 0000FFFF SPU lhu, read delay 6: 1447, value 0000FFFF SPU lhu, read delay 7: 1554, value 0000FFFF SPU lhu, read delay 8: 1645, value 0000FFFF SPU lhu, read delay 9: 1745, value 0000FFFF SPU lhu, read delay 10: 1845, value 0000FFFF SPU lhu, read delay 11: 1945, value 00000000 SPU lhu, read delay 12: 2045, value 00000000 SPU lhu, read delay 13: 2145, value 00000000 SPU lhu, read delay 14: 2245, value 00000000 SPU lhu, read delay 15: 2345, value 00000000 SPU lbu, read delay 0: 855, value 000000FF SPU lbu, read delay 1: 955, value 000000FF SPU lbu, read delay 2: 1055, value 000000FF SPU lbu, read delay 3: 1159, value 000000FF SPU lbu, read delay 4: 1255, value 000000FF SPU lbu, read delay 5: 1355, value 000000FF SPU lbu, read delay 6: 1455, value 000000FF SPU lbu, read delay 7: 1555, value 000000FF SPU lbu, read delay 8: 1655, value 000000FF SPU lbu, read delay 9: 1755, value 000000FF SPU lbu, read delay 10: 1855, value 000000FF SPU lbu, read delay 11: 1955, value 00000000 SPU lbu, read delay 12: 2055, value 00000000 SPU lbu, read delay 13: 2155, value 00000000 SPU lbu, read delay 14: 2256, value 00000000 SPU lbu, read delay 15: 2355, value 00000000 SPU lw, as set (200931E1): 4255, value 00000000 SPU lhu, as set (200931E1): 2245, value 00000000 SPU lbu, as set (200931E1): 2255, value 00000000 SPU lw, bit 8 flipped (200930E1): 3850, value 00000000 SPU lhu, bit 8 flipped (200930E1): 2245, value 00000000 SPU lbu, bit 8 flipped (200930E1): 2255, value 00000000 SPU lw, bit 9 flipped (200933E1): 4248, value 00000000 SPU lhu, bit 9 flipped (200933E1): 2245, value 00000000 SPU lbu, bit 9 flipped (200933E1): 2255, value 00000000 SPU lw, bit 10 flipped (200935E1): 4452, value 00000000 SPU lhu, bit 10 flipped (200935E1): 2251, value 00000000 SPU lbu, bit 10 flipped (200935E1): 2255, value 00000000 SPU lw, bit 11 flipped (200939E1): 4248, value 00000000 SPU lhu, bit 11 flipped (200939E1): 2245, value 00000000 SPU lbu, bit 11 flipped (200939E1): 2255, value 00000000 SPU lw, bit 12 flipped (200921E1): 8248, value 00000000 SPU lhu, bit 12 flipped (200921E1): 4251, value 00000000 SPU lbu, bit 12 flipped (200921E1): 2258, value 00000000 SPU lw, bit 13 flipped (200911E1): 4255, value 00000000 SPU lhu, bit 13 flipped (200911E1): 2245, value 00000000 SPU lbu, bit 13 flipped (200911E1): 2255, value 00000000 SPU lw, bit 29 flipped (000931E1): 4248, value 00000000 SPU lhu, bit 29 flipped (000931E1): 2251, value 00000000 SPU lbu, bit 29 flipped (000931E1): 2255, value 00000000 SPU lhu, bits 24-27 = F: 2245, value 00000000 SPU lhu, bits 24-27 = 2 (220931E1h): 2232, value 00000000 Done.