===== 12 FMR FU MDEC DMA RESET | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
MDEC by DMA after a reset, then a CPU store to a full input FIFO. Each step saves the
log first.
One decode by DMA, the reset writes, then DMA0 alone:
  Tables by DMA0: quant 16 words timeout, scale 32 words timeout; mono 8 bit decode of 1 block to DMA1: output word 0 CCCCCCCC, status A004000D (DMA1 timed out)
  Reset 80000000h: status A0040000
  MDEC1 80000000h: status before A0000000, after 80040000
  MDEC1 60000000h: status before 80040000, after 80040000
  MDEC0 40000000h: status before 80040000, after B004000F
  DMA0 alone, 16 words of quant: 77, 1 polls; status 8004FFFF, CHCR0 00000201 BCR0 00000010 MADR0 start64
A 33rd input word with bit 30 set:
  32 words written while bit 30 was clear, status E60400DF; the next word's store between timer 2 8 and 31; status then E60400DF; 0 words read out after, last 00000000, status E60400DF
Done.