===== 14 SMR F2 MDEC RESET | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
MDEC reset. Each row starts from a 15 bit decode with the input full (status read just
before, shown once), writes timer 2's mode, MDEC1 80000000h, then N nops, then reads
MDEC1 and timer 2. Run twice from the same state: cold, then warm. status@timer 2.
Status before the reset: E60400DF
  0 nops: cold E60400C0@13, warm E6040040@6
 10 nops: cold 80040000@29, warm 80040000@14
 20 nops: cold 80040000@56, warm 80040000@24
 30 nops: cold 80040000@74, warm 80040000@34
 40 nops: cold 80040000@107, warm 80040000@44
 50 nops: cold 80040000@123, warm 80040000@54
 60 nops: cold 80040000@149, warm 80040000@64
 70 nops: cold 80040000@168, warm 80040000@74
 80 nops: cold 80040000@195, warm 80040000@84
 90 nops: cold 80040000@213, warm 80040000@154
100 nops: cold 80040000@241, warm 80040000@104
110 nops: cold 80040000@258, warm 80040000@178
120 nops: cold 80040000@285, warm 80040000@134
130 nops: cold 80040000@303, warm 80040000@134
140 nops: cold 80040000@330, warm 80040000@144
150 nops: cold 80040000@348, warm 80040000@154
160 nops: cold 80040000@377, warm 80040000@200
170 nops: cold 80040000@393, warm 80040000@204
180 nops: cold 80040000@424, warm 80040000@235
190 nops: cold 80040000@442, warm 80040000@194
200 nops: cold 80040000@469, warm 80040000@204
Enables after a reset. From idle (a reset 2000 cycles before): MDEC1 80000000h, N nops,
MDEC1 60000000h, then MDEC1 and timer 2 read at once (status@timer 2); the status again
2000 cycles on; MDEC0 40000000h (luminance quant table) and the status; its 16 words by
DMA0 (cycles, or timeout after 200000 polls) and the status after. Run cold, then warm.
Enables rows, each with a DMA0 that times out if the enables were lost:
  Control, 60000000h 2000 cycles after the reset: 80040000, later 80040000, after the command B004000F, DMA0 90, then 8004FFFF
  Control, 00000000h (enables off) 2000 cycles after the reset: 80040000, later 80040000, after the command A004000F, DMA0 timeout, then A004000F
   0 nops, cold: 60000000@15, later 80040000, after the command A004000F, DMA0 timeout, then A004000F
   0 nops, warm: 60000000@8, later 80040000, after the command A004000F, DMA0 timeout, then A004000F
  10 nops, cold: 80040000@31, later 80040000, after the command B004000F, DMA0 84, then 8004FFFF
  10 nops, warm: 80040000@16, later 80040000, after the command B004000F, DMA0 94, then 8004FFFF
  20 nops, cold: 80040000@58, later 80040000, after the command B004000F, DMA0 89, then 8004FFFF
  20 nops, warm: 80040000@42, later 80040000, after the command B004000F, DMA0 94, then 8004FFFF
  40 nops, cold: 80040000@101, later 80040000, after the command B004000F, DMA0 84, then 8004FFFF
  40 nops, warm: 80040000@46, later 80040000, after the command B004000F, DMA0 84, then 8004FFFF
  80 nops, cold: 80040000@196, later 80040000, after the command B004000F, DMA0 88, then 8004FFFF
  80 nops, warm: 80040000@198, later 80040000, after the command B004000F, DMA0 84, then 8004FFFF
Done.