===== 16 SDS F2 DMA SPU COST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DMA4 SPU write, SyncMode 1, to 30000h, delay register 1F801014h = 200931E1h (it was
200931E1). Cycles from the CHCR write until bit 24 clears, three times each.
Blocks of 1 words x 256 (256 words): 16341 16337 16333
Blocks of 2 words x 128 (256 words): 16297 16296 16293
Blocks of 3 words x 85 (255 words): 16918 16910 16910
Blocks of 4 words x 64 (256 words): 18093 18056 18095
Blocks of 5 words x 51 (255 words): 17594 17598 17598
Blocks of 6 words x 42 (252 words): 17012 16999 16999
Blocks of 8 words x 32 (256 words): 17104 17053 17091
Blocks of 12 words x 21 (252 words): 15806 15819 15819
Blocks of 16 words x 16 (256 words): 16859 16872 16904
Blocks of 24 words x 10 (240 words): 10376 10411 10371
Blocks of 31 words x 8 (248 words): 8175 8174 8174
Blocks of 32 words x 8 (256 words): 8149 8178 8178
SyncMode 0, which the CPU cannot poll during:
  SyncMode 0, 256 words (BCR 00000100h, CHCR 01000001h): 1171 1116 1116; MADR then start+0, BCR 00000100, CHCR 00000001
Done.