===== 05 DSP DMA SPU TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DMA4 to and from sound RAM at 1000h: clocks from the CHCR write to bit 24 clear (polls meanwhile), three times each; MADR, BCR, CHCR after. SPU delay was 220931E1, 220931E1 here.
Write SyncMode 1, 16 words x 1: 219 (1) 221 (1) 217 (1) | MADR start64, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 2: 1498 (90) 1483 (88) 1286 (73) | MADR start128, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 4: 3836 (249) 3832 (249) 3847 (250) | MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 8: 8533 (571) 8545 (572) 8545 (572) | MADR start512, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16: 17780 (1202) 17783 (1202) 17790 (1202) | MADR start1024, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 64: 73072 (4969) 73079 (4970) 73079 (4970) | MADR start4096, BCR 00000010, CHCR 00000201
Write SyncMode 1, 1 word x 64: 4067 (264) 4084 (265) 4079 (265) | MADR start256, BCR 00000001, CHCR 00000201
Write SyncMode 1, 2 words x 32: 4867 (330) 4879 (331) 4870 (330) | MADR start256, BCR 00000002, CHCR 00000201
Write SyncMode 1, 4 words x 16: 4487 (299) 4478 (298) 4487 (299) | MADR start256, BCR 00000004, CHCR 00000201
Write SyncMode 1, 8 words x 8: 4278 (284) 4279 (284) 4486 (300) | MADR start256, BCR 00000008, CHCR 00000201
Read SyncMode 1, 16 words x 1: 215 (1) 219 (1) 214 (1) | MADR start64, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 4: 3901 (254) 3911 (254) 3913 (255) | MADR start256, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16: 17780 (1206) 17810 (1208) 17801 (1208) | MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 64: 73099 (5000) 73106 (5000) 73097 (5000) | MADR start4096, BCR 00000010, CHCR 00000200
Read SyncMode 1, 4 words x 16: 4786 (323) 4784 (323) 4784 (323) | MADR start256, BCR 00000004, CHCR 00000200
Write SyncMode 0, 16 words: 217 (1) 217 (1) 220 (1) | MADR start0, BCR 00000010, CHCR 00000001
Write SyncMode 0, 64 words: 601 (1) 609 (1) 606 (1) | MADR start0, BCR 00000040, CHCR 00000001
Write SyncMode 0, 256 words: 2137 (1) 2142 (1) 2138 (1) | MADR start0, BCR 00000100, CHCR 00000001
Write SyncMode 0 bit 28, 64 words: 601 (1) 608 (1) 606 (1) | MADR start0, BCR 00000040, CHCR 00000001
Read SyncMode 0, 64 words: 641 (3) 667 (5) 652 (4) | MADR start0, BCR 00000040, CHCR 00000000
Read SyncMode 0 bit 28, 64 words: 614 (1) 615 (1) 618 (1) | MADR start0, BCR 00000040, CHCR 00000000
Write SyncMode 1 bit 28, 16 words x 4: 3840 (250) 3841 (250) 3847 (250) | MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16, SPU delay 220931F1: 17775 (1201) 17339 (1167) 17781 (1202) | MADR start1024, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 16, SPU delay 220931F1: 17790 (1207) 17801 (1208) 17810 (1208) | MADR start1024, BCR 00000010, CHCR 00000200
Write SyncMode 1, 16 words x 16, SPU delay 22093141: 17431 (1173) 17642 (1190) 17651 (1191) | MADR start1024, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 16, delay 200931E1: 16874 (1215) 16868 (1214) 16868 (1214) | MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16, delay 220931E1: 17789 (1207) 17810 (1208) 17801 (1208) | MADR start1024, BCR 00000010, CHCR 00000200
64 words written then read back, SyncMode 1: 56 of 64 match
64 words written then read back, SyncMode 0: 16 of 64 match
Done.