===== 06 DMW DMA MIDWAY | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 1F801DAA CHCR, MADR, BCR and DICR polled while a transfer runs: a row each time one changes (t is timer 2's low 16 bits). DICR flags need bit 23 and bit 16+n (dmachannels.txt:184-186); bits 0-6 may give a flag per slice (dmachannels.txt:174-177). SPU write 16 words x 8, CHCR 01000201, DICR 00000000: poll t: CHCR MADR BCR DICR 0 553: 01000201 0011A428 00070010 00000000 3 1662: 01000201 0011A468 00060010 00000000 6 2740: 01000201 0011A4A8 00050010 00000000 10 4093: 01000201 0011A4E8 00040010 00000000 13 5160: 01000201 0011A528 00030010 00000000 16 6229: 01000201 0011A568 00020010 00000000 19 7293: 01000201 0011A568 00010010 00000000 20 7658: 01000201 0011A5A8 00010010 00000000 23 8726: 00000201 0011A5E8 00000010 00000000 done after 23 polls SPU write 16 words x 8, CHCR 11000201 (bit 28): poll t: CHCR MADR BCR DICR 0 520: 01000201 0011A428 00070010 00000000 4 1900: 01000201 0011A468 00060010 00000000 7 2961: 01000201 0011A4A8 00050010 00000000 10 4033: 01000201 0011A4E8 00040010 00000000 13 5101: 01000201 0011A4E8 00030010 00000000 14 5469: 01000201 0011A528 00030010 00000000 17 6540: 01000201 0011A568 00020010 00000000 20 7611: 01000201 0011A5A8 00010010 00000000 23 8685: 01000201 0011A5A8 00000010 00000000 24 9054: 00000201 0011A5E8 00000010 00000000 done after 24 polls SPU write 16 words x 8, DICR 00900000 (bit 23, bit 20): poll t: CHCR MADR BCR DICR 0 515: 01000201 0011A428 00070010 00900000 4 1903: 01000201 0011A468 00060010 00900000 7 2976: 01000201 0011A4A8 00050010 00900000 10 4040: 01000201 0011A4E8 00040010 00900000 13 5112: 01000201 0011A528 00030010 00900000 17 6465: 01000201 0011A568 00020010 00900000 20 7532: 01000201 0011A5A8 00010010 00900000 23 8602: 01000201 0011A5E8 00000010 90900000 24 8964: 00000201 0011A5E8 00000010 90900000 done after 24 polls I_STAT bit 3 after: 1 SPU write 16 words x 8, DICR 00900010 (bit 4 too, a flag per slice?): poll t: CHCR MADR BCR DICR 0 519: 01000201 0011A428 00070010 90900010 4 1901: 01000201 0011A468 00060010 90900010 7 2965: 01000201 0011A4A8 00050010 90900010 10 4037: 01000201 0011A4E8 00040010 90900010 13 5105: 01000201 0011A4E8 00030010 90900010 14 5473: 01000201 0011A528 00030010 90900010 17 6544: 01000201 0011A568 00020010 90900010 20 7615: 01000201 0011A5A8 00010010 90900010 23 8689: 01000201 0011A5A8 00000010 90900010 24 9058: 00000201 0011A5E8 00000010 90900010 done after 24 polls I_STAT bit 3 after: 1 SPU write 16 words x 8, DICR 00900010, I_STAT bit 3 in the last column: poll t: CHCR MADR BCR I_STAT&8 0 519: 01000201 0011A428 00070010 00000008 4 1913: 01000201 0011A468 00060010 00000008 7 2985: 01000201 0011A4A8 00050010 00000008 10 4059: 01000201 0011A4E8 00040010 00000008 13 5112: 01000201 0011A528 00030010 00000008 17 6462: 01000201 0011A568 00020010 00000008 20 7521: 01000201 0011A5A8 00010010 00000008 23 8590: 01000201 0011A5E8 00000010 00000008 24 8952: 00000201 0011A5E8 00000010 00000008 done after 24 polls SPU read 16 words x 8, CHCR 01000200: poll t: CHCR MADR BCR DICR 0 519: 01000200 0011A428 00070010 00000000 4 1907: 01000200 0011A468 00060010 00000000 7 2969: 01000200 0011A4A8 00050010 00000000 10 4034: 01000200 0011A4E8 00040010 00000000 13 5108: 01000200 0011A4E8 00030010 00000000 14 5475: 01000200 0011A528 00030010 00000000 17 6550: 01000200 0011A568 00020010 00000000 20 7622: 01000200 0011A5A8 00010010 00000000 23 8675: 00000200 0011A5E8 00000010 00000000 done after 23 polls GPU write 16 words x 8 to VRAM, CHCR 01000201: poll t: CHCR MADR BCR DICR 0 552: 01000201 0015B5E8 00000010 00000000 1 941: 00000201 0015B5E8 00000010 00000000 done after 1 polls GPU list 8 nodes of 15 NOPs, DICR 00840004 (bit 2, a flag per entry?): list at 116248, nodes 64 bytes apart poll t: CHCR MADR BCR DICR 0 573: 01000401 00FFFFFF 00000000 84840004 1 964: 00000401 00FFFFFF 00000000 84840004 done after 1 polls Done.