===== 11 TMR TIMERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A timers test Detected NTSC system. Forced NTSC system. Timer0, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer0, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer0, clock: System clock, frame delay: 106459, 107363, 107335, 107352, 107339, 107355, 107325, 107343, 107349, 107339, Timer0, clock: Dot clock, 1000 cycles delay: 200, 199, 200, 200, 200, 200, 201, 201, 200, 200, Timer0, clock: Dot clock, 5000 cycles delay: 991, 992, 992, 991, 992, 992, 992, 992, 992, 991, Timer0, clock: Dot clock, frame delay: 111935, 112035, 112032, 112033, 112035, 112029, 112036, 112031, 112038, 112029, Timer1, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer1, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer1, clock: System clock, frame delay: 106859, 107349, 107369, 107325, 107349, 107335, 107350, 107368, 107332, 107342, Timer1, clock: Hblank, 1000 cycles delay: 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, Timer1, clock: Hblank, 5000 cycles delay: 2, 2, 3, 2, 2, 2, 2, 3, 2, 2, Timer1, clock: Hblank, frame delay: 263, 263, 263, 263, 263, 263, 263, 263, 263, 263, Timer2, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer2, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer2, clock: System clock, frame delay: 106869, 107339, 107349, 107343, 107335, 107371, 107320, 107357, 107344, 107335, Timer2, clock: System clock/8, 1000 cycles delay: 126, 126, 127, 126, 126, 127, 126, 127, 126, 126, Timer2, clock: System clock/8, 5000 cycles delay: 627, 626, 626, 627, 626, 627, 626, 626, 627, 626, Timer2, clock: System clock/8, frame delay: 70701, 70766, 70757, 70762, 70763, 70758, 70766, 70757, 70763, 70761, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs) 0 = Pause counter during Hblanks 306, 428, 550, 572, 572, 572, 572, 622, 744, 866, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 105, 227, 349, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs) 0 = Pause counter during Hblanks 290, 412, 459, 459, 459, 459, 483, 605, 727, 849, 1 = Reset counter to 0 at Hblanks 254, 376, 39, 161, 283, 405, 527, 649, 771, 893, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 42, 164, 286, 408, 530, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 58, 180, 302, 424, 546, 668, 790, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs) 0 = Pause counter during Hblanks 294, 416, 538, 660, 782, 904, 1026, 1148, 1270, 1392, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 79, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 45, 167, 289, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs) 0 = Pause counter during Hblanks 299, 421, 519, 519, 519, 519, 519, 614, 736, 858, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 115, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs) 0 = Pause counter during Hblanks 285, 407, 529, 651, 773, 895, 1017, 1139, 1151, 1151, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 118, 240, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs) 0 = Pause counter during Hblanks 45, 65, 84, 103, 123, 142, 158, 158, 158, 158, 1 = Reset counter to 0 at Hblanks 38, 57, 77, 96, 115, 135, 154, 173, 193, 212, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs) 0 = Pause counter during Hblanks 59, 83, 107, 131, 155, 180, 204, 214, 214, 214, 1 = Reset counter to 0 at Hblanks 48, 72, 96, 120, 145, 169, 193, 217, 241, 265, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 47, 71, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 39, 63, 87, 111, 136, 160, 184, 208, 232, 256, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs) 0 = Pause counter during Hblanks 68, 95, 123, 151, 178, 206, 233, 252, 252, 252, 1 = Reset counter to 0 at Hblanks 54, 82, 109, 137, 164, 192, 220, 247, 275, 303, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 6, 33, 60, 88, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 8, 35, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs) 0 = Pause counter during Hblanks 0, 0, 4, 42, 81, 120, 158, 197, 236, 274, 1 = Reset counter to 0 at Hblanks 76, 115, 154, 192, 231, 270, 308, 347, 386, 424, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 25, 63, 102, 140, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs) 0 = Pause counter during Hblanks 120, 168, 216, 265, 313, 361, 369, 369, 369, 369, 1 = Reset counter to 0 at Hblanks 95, 143, 191, 240, 288, 336, 385, 433, 481, 530, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 24, 72, 121, 169, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer1 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Pause counter during Vblanks 285, 407, 529, 651, 773, 895, 1017, 1139, 1261, 1383, 1 = Reset counter to 0 at Vblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Vblanks and pause outside of Vblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Vblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer1 sync modes (clock source = Hblank, 100 delay cycles, not resetted between runs) 0 = Pause counter during Vblanks 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1 = Reset counter to 0 at Vblanks 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2 = Reset counter to 0 at Vblanks and pause outside of Vblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Vblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 = Free Run 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Free Run 254, 376, 498, 620, 742, 864, 986, 1108, 1230, 1352, 3 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 = Free Run 239, 361, 483, 605, 727, 849, 971, 1093, 1215, 1337, 2 = Free Run 239, 361, 483, 605, 727, 849, 971, 1093, 1215, 1337, 3 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Check when Timer2 counter (System clock) is reset when reaching target (= 10). counter == 0, 1665 ticks counter == 1, 836 ticks counter == 2, 833 ticks counter == 3, 831 ticks counter == 4, 837 ticks counter == 5, 833 ticks counter == 6, 831 ticks counter == 7, 835 ticks counter == 8, 833 ticks counter == 9, 831 ticks counter == 10, 835 ticks <<<< This value should be non-zero counter == 11, 0 ticks Reached target: 1 (ok) Reached 0xFFFF: 0 (ok) Counter reset AFTER reaching target: 1 (ok) Target + 1 not reached: 1 (ok) Check if write to mode register acknowledges the targetReached flag Write 0x0000 to Timer0.mode, read 0x0400 Write 0xffff to Timer0.mode, read 0x07ff Read mode after waiting for targetReached: 0x1c08 Read again: 0x0408 Write mode after waiting for targetReached and then read: 0x1c08 Read again: 0x0408 Done.