===== 04 SRT SPU READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 1F801DAA SPU reads at 1F801C00, SPU delay 220931E1: SPU lw, read delay 0: 1449, value FFFFFFFF SPU lw, read delay 1: 1644, value FFFFFFFF SPU lw, read delay 2: 1839, value FFFFFFFF SPU lw, read delay 3: 2039, value FFFFFFFF SPU lw, read delay 4: 2239, value FFFFFFFF SPU lw, read delay 5: 2439, value FFFFFFFF SPU lw, read delay 6: 2639, value FFFFFFFF SPU lw, read delay 7: 2839, value FFFFFFFF SPU lw, read delay 8: 3039, value FFFFFFFF SPU lw, read delay 9: 3254, value FFFFFFFF SPU lw, read delay 10: 3439, value FFFFFFFF SPU lw, read delay 11: 3639, value 00000000 SPU lw, read delay 12: 3839, value 00000000 SPU lw, read delay 13: 4039, value 00000000 SPU lw, read delay 14: 4239, value 00000000 SPU lw, read delay 15: 4439, value 00000000 SPU lhu, read delay 0: 852, value 0000FFFF SPU lhu, read delay 1: 937, value 0000FFFF SPU lhu, read delay 2: 1052, value 0000FFFF SPU lhu, read delay 3: 1137, value 0000FFFF SPU lhu, read delay 4: 1237, value 0000FFFF SPU lhu, read delay 5: 1337, value 0000FFFF SPU lhu, read delay 6: 1437, value 0000FFFF SPU lhu, read delay 7: 1537, value 0000FFFF SPU lhu, read delay 8: 1637, value 0000FFFF SPU lhu, read delay 9: 1737, value 0000FFFF SPU lhu, read delay 10: 1837, value 0000FFFF SPU lhu, read delay 11: 1937, value 00000000 SPU lhu, read delay 12: 2037, value 00000000 SPU lhu, read delay 13: 2137, value 00000000 SPU lhu, read delay 14: 2237, value 00000000 SPU lhu, read delay 15: 2337, value 00000000 SPU lbu, read delay 0: 844, value 000000FF SPU lbu, read delay 1: 941, value 000000FF SPU lbu, read delay 2: 1041, value 000000FF SPU lbu, read delay 3: 1141, value 000000FF SPU lbu, read delay 4: 1241, value 000000FF SPU lbu, read delay 5: 1341, value 000000FF SPU lbu, read delay 6: 1444, value 000000FF SPU lbu, read delay 7: 1541, value 000000FF SPU lbu, read delay 8: 1641, value 000000FF SPU lbu, read delay 9: 1741, value 000000FF SPU lbu, read delay 10: 1841, value 000000FF SPU lbu, read delay 11: 1941, value 00000000 SPU lbu, read delay 12: 2041, value 00000000 SPU lbu, read delay 13: 2141, value 00000000 SPU lbu, read delay 14: 2241, value 00000000 SPU lbu, read delay 15: 2341, value 00000000 SPU lw, as set (220931E1): 4244, value 00000000 SPU lhu, as set (220931E1): 2252, value 00000000 SPU lbu, as set (220931E1): 2241, value 00000000 SPU lw, bit 8 flipped (220930E1): 3844, value 00000000 SPU lhu, bit 8 flipped (220930E1): 2237, value 00000000 SPU lbu, bit 8 flipped (220930E1): 2241, value 00000000 SPU lw, bit 9 flipped (220933E1): 4244, value 00000000 SPU lhu, bit 9 flipped (220933E1): 2237, value 00000000 SPU lbu, bit 9 flipped (220933E1): 2241, value 00000000 SPU lw, bit 10 flipped (220935E1): 4842, value 00000000 SPU lhu, bit 10 flipped (220935E1): 2455, value 00000000 SPU lbu, bit 10 flipped (220935E1): 2445, value 00000000 SPU lw, bit 11 flipped (220939E1): 4244, value 00000000 SPU lhu, bit 11 flipped (220939E1): 2237, value 00000000 SPU lbu, bit 11 flipped (220939E1): 2244, value 00000000 SPU lw, bit 12 flipped (220921E1): 8249, value 00000000 SPU lhu, bit 12 flipped (220921E1): 4237, value 00000000 SPU lbu, bit 12 flipped (220921E1): 2241, value 00000000 SPU lw, bit 13 flipped (220911E1): 4244, value 00000000 SPU lhu, bit 13 flipped (220911E1): 2237, value 00000000 SPU lbu, bit 13 flipped (220911E1): 2244, value 00000000 SPU lw, bit 29 flipped (020931E1): 4246, value 00000000 SPU lhu, bit 29 flipped (020931E1): 2237, value 00000000 SPU lbu, bit 29 flipped (020931E1): 2241, value 00000000 SPU lhu, bits 24-27 = F: 2242, value 00000000 SPU lhu, bits 24-27 = 2 (220931E1h): 2237, value 00000000 Done.