===== 08 RC8 TIMER SYNC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Timer0 sysclock free, cycles between two hblank ticks: 2140 2154 2154 2154 2143 2154 2143 2154
Timer0 sysclock sync 0 (pause in hblank), counted between two ticks: 1614 1614 1614 1614 1614 1614 1614 1613
Timer0 sysclock sync 1 (reset at hblank), value at a tick: 1634 1627 1631 1624 1628 1632 1625 1629
Timer0 sysclock sync 2 (count in hblank only), value at a tick: 16 9 13 17 15 19 12 16
Timer0 dotclock sync 0, dots counted between two ticks: 639 639 639 639 639 639 639 639
Timer0 dotclock sync 1, value at a tick: 646 644 641 642 644 641 643 644
Timer1 sysclock sync 1 (reset at vblank), value at the vblank IRQ: 55470 57885 57877 57881
Timer1 sysclock sync 2 (count in vblank), 20000 cycles after the IRQ: 20169 20117 20102 20109
Timer1 sysclock sync 2, 100000 cycles after the IRQ: 0 0 0 0
Timer1 hblank sync 2, lines 100000 cycles after the IRQ: 0 0 0 0
Timer1 hblank sync 0 (pause in vblank), lines from one IRQ to the next: 239 239 239 239
Timer1 hblank free, lines from one IRQ to the next: 263 263 263 263
Timer1 hblank sync 1, value at the vblank IRQ: 237 237 237 237
Timer0 sysclock sync 3: mode 0407 at once, 0407 5000 cycles on, counter then 3578
Timer0 dotclock sync 3: mode 0507 at once, 0507 5000 cycles on, counter then 1941
Timer1 sysclock sync 3: mode 0407 at once, 0407 5000 cycles after the vblank, counter then 0
Timer1 hblank sync 3: mode 0507 at once, 0507 5000 cycles after the vblank, counter then 240
Timer2 sysclock sync 3: mode 0407 at once, 0407 5000 cycles after the vblank, counter then 0
Timer2 sysclock sync 1: mode 0403 at once, 0403 5000 cycles on, counter then 5155
Timer1 sysclock sync 0: mode 0401 at once, 1C01 5000 cycles after the vblank, counter then 28484
Done.