===== 01 DRM D2 REGISTER BITS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Each register written one bit at a time and read back, each channel with its DPCR
enable off (channels.txt:18-87). CHCR is written 0 before any enable comes back.
Channel 0:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 1:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 2:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 3:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 4:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 5:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR keeps 71770703; FFFFFFFFh reads 71770703; 0 reads 00000000
Channel 6:
  MADR keeps 00FFFFFF; FFFFFFFFh reads 00FFFFFF; 0 reads 00000000
  BCR keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF; 0 reads 00000000
  CHCR bit 0 written reads 00000002
  CHCR bit 2 written reads 00000002
  CHCR keeps 51000002; FFFFFFFFh reads 51000002; 0 reads 00000002
DPCR one bit at a time (every CHCR 0):
  keeps FFFFFFFF; FFFFFFFFh reads FFFFFFFF
DICR bits 0-23 one at a time, with I_STAT bit 3 after each (bit 15 forces it):
  0:00000001/0  1:00000002/0  2:00000004/0  3:00000008/0
  4:00000010/0  5:00000020/0  6:00000000/0  7:00000000/0
  8:00000000/0  9:00000000/0 10:00000000/0 11:00000000/0
 12:00000000/0 13:00000000/0 14:00000000/0 15:80008000/1
 16:00010000/0 17:00020000/0 18:00040000/0 19:00080000/0
 20:00100000/0 21:00200000/0 22:00400000/0 23:00800000/0
DICR 80000000h (bit 31 written) reads 00000000
DICR 7F000000h (every flag written 1, none set) reads 00000000
Done.