===== 01 SDI F2 DICR POLL | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
DICR written with timer 2 zeroed just before it. Interrupts off (SR IEc 0) throughout.
DICR 0 is the scale: its loop runs all 300 turns, so timer 2 over 300 gives one turn.
I_STAT bit 3, a loop of one I_STAT load a turn (lw, addiu, andi, sltiu, sltu, and, bnez, nop):
  DICR 00000000: the bit never set in 300 turns; timer 2 after them 3622
  DICR 00008000: the bit was set on turn 2; timer 2 after the loop 24
  DICR 00008000: the bit was set on turn 2; timer 2 after the loop 24
  DICR 00008000: the bit was set on turn 2; timer 2 after the loop 24
I_STAT bit 3, eight I_STAT loads back to back:
  DICR 00000000: I_STAT bit 3 after each of the 8 loads: 0 0 0 0 0 0 0 0; timer 2 after them 53
  DICR 00008000: I_STAT bit 3 after each of the 8 loads: 0 0 1 1 1 1 1 1; timer 2 after them 32
  DICR 00008000: I_STAT bit 3 after each of the 8 loads: 0 0 1 1 1 1 1 1; timer 2 after them 32
  DICR 00008000: I_STAT bit 3 after each of the 8 loads: 0 0 1 1 1 1 1 1; timer 2 after them 32
CAUSE.IP2, a loop of one mfc0 CAUSE a turn (the same loop), I_MASK 00000008:
  DICR 00000000: the bit never set in 300 turns; timer 2 after them 2420
  DICR 00008000: the bit was set on turn 2; timer 2 after the loop 16
  DICR 00008000: the bit was set on turn 2; timer 2 after the loop 16
  DICR 00008000: the bit was set on turn 2; timer 2 after the loop 16
CAUSE.IP2, eight mfc0 CAUSE back to back, I_MASK 00000008:
  DICR 00000000: CAUSE.IP2 after each of the 8 loads: 0 0 0 0 0 0 0 0; timer 2 after them 25
  DICR 00008000: CAUSE.IP2 after each of the 8 loads: 0 0 0 0 0 0 0 1; timer 2 after them 8
  DICR 00008000: CAUSE.IP2 after each of the 8 loads: 0 0 0 0 0 0 0 1; timer 2 after them 8
  DICR 00008000: CAUSE.IP2 after each of the 8 loads: 0 0 0 0 0 0 0 1; timer 2 after them 8
DICR was 00000000 and is back to 0, then its enables.
Done.