===== 14 SMR F2 MDEC RESET | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
MDEC reset. Each row starts from a 15 bit decode with the input full (status read just
before, shown once), writes timer 2's mode, MDEC1 80000000h, then N nops, then reads
MDEC1 and timer 2. Run twice from the same state: cold, then warm. status@timer 2.
Status before the reset: E60400DF
  0 nops: cold E6040040@13, warm E6040040@6
 10 nops: cold 80040000@34, warm 80040000@14
 20 nops: cold 80040000@55, warm 80040000@24
 30 nops: cold 80040000@74, warm 80040000@34
 40 nops: cold 80040000@100, warm 80040000@44
 50 nops: cold 80040000@124, warm 80040000@54
 60 nops: cold 80040000@149, warm 80040000@64
 70 nops: cold 80040000@169, warm 80040000@74
 80 nops: cold 80040000@192, warm 80040000@84
 90 nops: cold 80040000@214, warm 80040000@159
100 nops: cold 80040000@236, warm 80040000@104
110 nops: cold 80040000@258, warm 80040000@178
120 nops: cold 80040000@284, warm 80040000@134
130 nops: cold 80040000@303, warm 80040000@134
140 nops: cold 80040000@331, warm 80040000@144
150 nops: cold 80040000@352, warm 80040000@154
160 nops: cold 80040000@374, warm 80040000@201
170 nops: cold 80040000@397, warm 80040000@209
180 nops: cold 80040000@423, warm 80040000@228
190 nops: cold 80040000@442, warm 80040000@194
200 nops: cold 80040000@465, warm 80040000@204
Enables after a reset. From idle (a reset 2000 cycles before): MDEC1 80000000h, N nops,
MDEC1 60000000h, then MDEC1 and timer 2 read at once (status@timer 2); the status again
2000 cycles on; MDEC0 40000000h (luminance quant table) and the status; its 16 words by
DMA0 (cycles, or timeout after 200000 polls) and the status after. Run cold, then warm.
Enables rows, each with a DMA0 that times out if the enables were lost: not run in this table.
Done.