===== 15 SDS F2 DMA SPU COST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
DMA4 SPU write, SyncMode 1, to 30000h, delay register 1F801014h = 200931E1h (it was
200931E1). Cycles from the CHCR write until bit 24 clears, three times each.
Blocks of 1 words x 256 (256 words): 16346 16346 16338
Blocks of 2 words x 128 (256 words): 16301 16301 16301
Blocks of 3 words x 85 (255 words): 16245 16389 16347
Blocks of 4 words x 64 (256 words): 18070 18069 18069
Blocks of 5 words x 51 (255 words): 17597 17608 17601
Blocks of 6 words x 42 (252 words): 17024 17012 17012
Blocks of 8 words x 32 (256 words): 17067 17072 17072
Blocks of 12 words x 21 (252 words): 15809 15809 15809
Blocks of 16 words x 16 (256 words): 16883 16883 16883
Blocks of 24 words x 10 (240 words): 10425 10383 10383
Blocks of 31 words x 8 (248 words): 8170 8135 8133
Blocks of 32 words x 8 (256 words): 8160 8202 8202
SyncMode 0, which the CPU cannot poll during: not run in this table.
Done.