===== 03 FVB FU T1 VBLANK EDGE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
Timer1 sync mode 1 (reset at vblank), set at the vblank IRQ (I_STAT bit 0); timer 2
counts system cycles from then. Where timer 1 first reads lower than before is the reset.
Timer1 system clock, sync mode 1 (mode 0003h):
  Timer1 read 49424 then 10 at 49457 cycles after the vblank IRQ (the read before at 49416)
  Timer1 read 49450 then 30 at 49495 cycles after the vblank IRQ (the read before at 49454)
  Timer1 read 49453 then 28 at 49498 cycles after the vblank IRQ (the read before at 49457)
  Timer1 read 49453 then 27 at 49498 cycles after the vblank IRQ (the read before at 49457)
Timer1 hblank clock, sync mode 1 (mode 0103h):
  Timer1 read 24 then 0 at 52034 cycles after the vblank IRQ (the read before at 51993)
  Timer1 read 24 then 0 at 52044 cycles after the vblank IRQ (the read before at 52003)
  Timer1 read 24 then 0 at 52036 cycles after the vblank IRQ (the read before at 51995)
  Timer1 read 24 then 0 at 52040 cycles after the vblank IRQ (the read before at 51999)
Timer1 hblank clock free run (mode 0100h) zeroed at one vblank IRQ, read at the next: 263 263 263 263
Done.