===== 07 FSP FU SPU ENV FIFO | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
Envelope counter, one for all voices or one each: voices 0 and 1 attack linear shift
16 step 0, keyed on 1500 cycles apart; cycles from voice 0's KON.
Voice 0 keyed on at 0, voice 1 at 1636; first level changes, voice 0: 11022 35590 60142 84702; voice 1: 11022 35590 60142 84702; levels then 002A 002A
Voice 0 keyed on at 0, voice 1 at 1592; first level changes, voice 0: 17885 42429 67077 91629; voice 1: 17885 42429 67077 91629; levels then 002A 002A
Voice 0 keyed on at 0, voice 1 at 1568; first level changes, voice 0: 17866 42418 66977 91618; voice 1: 17866 42418 66977 91618; levels then 002A 002A
ADSR level times the sample: tone T on voice 1, pitch 1000h, held at 7FFFh; the level
register written, then the voice 1 capture buffer (first 16 samples).
Level as it stands, 255 changes in 256:
  FC83 FD03 FD82 FE01 FE81 FF00 FF80 FFFF 007E 00FE 017D 01FD 027C 02FC 024B FD30
Level read 3FFF
Level written 4000h, reads 4000
Level 4000h, 255 changes in 256:
  007F 00FE 017E 01FD 027D 02FC 024C FD30 FC83 FD03 FD88 FE28 FEC5 FF57 FFE1 0062
Level written 7FFFh, reads 7FFF
Level 7FFFh, 255 changes in 256:
  F907 FA06 FB11 FC50 FD8A FEAF FFC3 00C4 01B6 0299 036E 0436 04F1 05A1 0645 06DF
FIFO drain: halfwords B000h, B001h, .. to scratch at 30000h (filled EEEEh) by one DMA
block of 16 words, a wait, SPUCNT transfer mode Stop, then read back by DMA.
Wait 0 cycles after the DMA ended: 9 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 100 cycles after the DMA ended: 9 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 200 cycles after the DMA ended: 10 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 300 cycles after the DMA ended: 15 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 400 cycles after the DMA ended: 18 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 500 cycles after the DMA ended: 23 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 600 cycles after the DMA ended: 27 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 700 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 800 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 900 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1000 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1100 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1200 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1300 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1400 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1500 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1600 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Start address one 8 byte unit past a block (spuenv END's S4+8 case): tone T on voice 1,
pitch 1000h, start and repeat as given; the voice 1 capture buffer.
Start 40C0h (the block), 66 changes in 256:
  0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
  0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Start 40C1h (one unit in), 255 changes in 256:
  FE29 FDC7 FD6A FD14 FD4A FF98 007E 00FE 017D 01FD 027C 02FC 024B FD30 FC83 FD03
  FD82 FE01 FE81 FF00 FF80 FFFF 007E 00FE 017D 01FD 027C 02FC 024B FD30 FC83 FD03
Done.