===== 08 TWR T3 WRITES COUNTING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Each timer at the system clock, mode 0058h (reset at target, IRQ at target, repeat),
target 8000h, counted up to about 4000h, then one write. The counter read three times
at once, then cycles from the write to the first mode read with bit 11 and with bit
12, and to I_STAT (0 = not within 150000). timers.txt:7-10, :56-58.
T0 counter written 0000: counter 0019 0027 002C; bit 11 at 32870, bit 12 at 0, I_STAT at 32870
T0 counter written 3FF0: counter 4000 400E 4013; bit 11 at 16438, bit 12 at 0, I_STAT at 16438
T0 counter written 7FF0: counter 8000 000C 0011; bit 11 at 124, bit 12 at 0, I_STAT at 124
T0 counter written 8000: counter 000E 001C 0021; bit 11 at 124, bit 12 at 0, I_STAT at 124
T0 counter written 8001: counter 8011 801F 8024; bit 11 at 65620, bit 12 at 32841, I_STAT at 65620
T0 counter written FFF0: counter 0000 000E 0013; bit 11 at 32868, bit 12 at 124, I_STAT at 32868
T0 counter written FFFF: counter 000F 001D 0022; bit 11 at 65618, bit 12 at 124, I_STAT at 32793
T0 target written 2000: counter 408F 409D 40A2; bit 11 at 57313, bit 12 at 49104, I_STAT at 57313
T0 target written 4000: counter 4078 4086 408B; bit 11 at 65489, bit 12 at 49091, I_STAT at 65489
T0 target written 4040: counter 4077 4085 408A; bit 11 at 65575, bit 12 at 49092, I_STAT at 65575
T0 target written 4400: counter 4081 408F 4094; bit 11 at 998, bit 12 at 0, I_STAT at 998
T0 target written FFFF: counter 4077 4085 408A; bit 11 at 49090, bit 12 at 49090, I_STAT at 49090
T0 mode written 0058: counter 0010 001E 0023; bit 11 at 32839, bit 12 at 0, I_STAT at 32839
T0 mode written 0050: counter 0010 001E 0027; bit 11 at 32838, bit 12 at 65608, I_STAT at 32838
T1 counter written 0000: counter 0010 001E 0023; bit 11 at 32851, bit 12 at 0, I_STAT at 32851
T1 counter written 3FF0: counter 4000 400E 4013; bit 11 at 16432, bit 12 at 0, I_STAT at 16432
T1 counter written 7FF0: counter 8000 000C 0011; bit 11 at 124, bit 12 at 0, I_STAT at 124
T1 counter written 8000: counter 000E 001C 0021; bit 11 at 124, bit 12 at 0, I_STAT at 124
T1 counter written 8001: counter 8011 801F 8024; bit 11 at 65625, bit 12 at 32841, I_STAT at 65625
T1 counter written FFF0: counter 0000 000E 0013; bit 11 at 32878, bit 12 at 124, I_STAT at 32799
T1 counter written FFFF: counter 0014 0022 0027; bit 11 at 32798, bit 12 at 129, I_STAT at 32798
T1 target written 2000: counter 4082 4090 4095; bit 11 at 57295, bit 12 at 49081, I_STAT at 57295
T1 target written 4000: counter 4077 4085 408A; bit 11 at 65505, bit 12 at 49101, I_STAT at 65505
T1 target written 4040: counter 4077 4085 408A; bit 11 at 65567, bit 12 at 49090, I_STAT at 65567
T1 target written 4400: counter 4077 4085 408A; bit 11 at 988, bit 12 at 0, I_STAT at 988
T1 target written FFFF: counter 407C 408A 4093; bit 11 at 49088, bit 12 at 49088, I_STAT at 49088
T1 mode written 0058: counter 0010 001E 0023; bit 11 at 32848, bit 12 at 0, I_STAT at 32848
T1 mode written 0050: counter 0010 001E 0023; bit 11 at 32844, bit 12 at 65610, I_STAT at 32844
T2 counter written 0000: counter 0010 001F 0024; bit 11 at 32846, bit 12 at 0, I_STAT at 32846
T2 counter written 3FF0: counter 4000 400E 4013; bit 11 at 16432, bit 12 at 0, I_STAT at 16432
T2 counter written 7FF0: counter 8000 000C 0011; bit 11 at 124, bit 12 at 0, I_STAT at 124
T2 counter written 8000: counter 000E 001C 0021; bit 11 at 124, bit 12 at 0, I_STAT at 124
T2 counter written 8001: counter 8011 801F 8024; bit 11 at 65625, bit 12 at 32841, I_STAT at 65625
T2 counter written FFF0: counter 0000 000E 0013; bit 11 at 32878, bit 12 at 124, I_STAT at 32799
T2 counter written FFFF: counter 000F 001D 0022; bit 11 at 65618, bit 12 at 124, I_STAT at 32793
T2 target written 2000: counter 4087 4095 409A; bit 11 at 57300, bit 12 at 49095, I_STAT at 57300
T2 target written 4000: counter 4077 4085 408A; bit 11 at 65505, bit 12 at 49101, I_STAT at 65505
T2 target written 4040: counter 4077 4085 408A; bit 11 at 65567, bit 12 at 49090, I_STAT at 65567
T2 target written 4400: counter 4077 4085 408A; bit 11 at 988, bit 12 at 0, I_STAT at 988
T2 target written FFFF: counter 407C 408A 4093; bit 11 at 49088, bit 12 at 49088, I_STAT at 49088
T2 mode written 0058: counter 0010 001E 0023; bit 11 at 32848, bit 12 at 0, I_STAT at 32848
T2 mode written 0050: counter 0010 001E 0023; bit 11 at 32844, bit 12 at 65610, I_STAT at 32844
Counter written 1234h on a running timer 2 (mode 0000h), then six reads back to back: 1234 1241 124D 125C 1271 1284
The same on timer 2 at the system clock / 8 (mode 0200h): 1234 1254 1264 1274 1284 1294 (8 cycles apart)
Done.