===== 03 DIC D2 DICR CHANNELS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
DICR written as shown (flags cleared), one transfer of each kind, then DICR and
I_STAT bit 3 (channels.txt:112-130). Per kind: DICR 0, the channel's enable bit
16+n alone, with bit 23, and bit 23 alone. Clocks between.
OTC (channel 6): 00000000 -> 153 00000000/0 00400000 -> 105 40400000/0
  00C00000 -> 105 C0C00000/1 00800000 -> 105 00800000/0
GPU write (channel 2): 00000000 -> 155 00000000/0 00040000 -> 146 04040000/0
  00840000 -> 146 84840000/1 00800000 -> 155 00800000/0
SPU write (channel 4): 00000000 -> 3805 00000000/0 00100000 -> 3512 10100000/0
  00900000 -> 3499 90900000/1 00800000 -> 3504 00800000/0
MDEC0 table (channel 0): 00000000 -> 52 00000000/0 00010000 -> 52 01010000/0
  00810000 -> 52 81810000/1 00800000 -> 52 00800000/0
MDEC1 block (channel 1): 00000000 -> 870 00000000/0 00020000 -> 870 02020000/0
  00820000 -> 870 82820000/1 00800000 -> 870 00800000/0
A transfer stopped by writing CHCR bit 24 = 0 part way, enable and bit 23 set:
SPU write of 1024 words stopped at 3000: MADR moved 192, BCR 003D0010 (003D0010 5000 later), CHCR 00000201, DICR 00900000, IRQ3 0
  started again with the same CHCR: 69458, MADR moved 4096, BCR 00000010, DICR 90900000
GPU write of 1024 words stopped at 1000: MADR moved 2432, BCR 001A0010 (001A0010 5000 later), CHCR 00000201, DICR 00840000, IRQ3 0
  started again with the same CHCR: 752, MADR moved 4096, BCR 00000010, DICR 84840000
Bit 15 forced twice, with I_STAT bit 3 acknowledged between; then 0 and again:
 first IRQ3 0, second (bit 15 still set) 1, after 0 then 8000h 0, DICR 80008000
A flag set with bit 23 off (OTC, enable bit 22 alone), then bit 23 written on:
 after the OTC 40400000; bit 23 on C0C00000, IRQ3 1; flag written 1 00C00000
Flag written 0 keeps it? OTC with 22 and 23, then DICR written 00C00000h:
 after the OTC C0C00000; 00C00000h written C0C00000; bit 23 off 40400000
Done.