===== 04 DCI D2 IRQ LATENCY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Clocks from the CHCR write to CHCR bit 24 clear, to the DICR flag, and to I_STAT
bit 3, with the channel's enable and bit 23 set (FINDINGS "DICR latency"). The
poll takes three reads a turn; the I_STAT-only rows poll one register. Three each.
OTC 16: bit 24 clear 79, flag 79, I_STAT 79
OTC 256: bit 24 clear 322, flag 322, I_STAT 322
OTC 16, I_STAT only: I_STAT 99
GPU write 16: bit 24 clear 78, flag 78, I_STAT 78
GPU write 64: bit 24 clear 136, flag 136, I_STAT 136
GPU write 16, I_STAT only: I_STAT 107
SPU write 16: bit 24 clear 180, flag 180, I_STAT 180
SPU write 64: bit 24 clear 3539, flag 3539, I_STAT 3319
SPU write 16, I_STAT only: I_STAT 211
MDEC0 table 16: bit 24 clear 66, flag 66, I_STAT 66
MDEC1 block 16: bit 24 clear 837, flag 837, I_STAT 837
MDEC1 block 16, I_STAT only: I_STAT 876
OTC 16: bit 24 clear 67, flag 67, I_STAT 67
OTC 256: bit 24 clear 322, flag 322, I_STAT 322
OTC 16, I_STAT only: I_STAT 99
GPU write 16: bit 24 clear 80, flag 80, I_STAT 80
GPU write 64: bit 24 clear 136, flag 136, I_STAT 136
GPU write 16, I_STAT only: I_STAT 107
SPU write 16: bit 24 clear 180, flag 180, I_STAT 180
SPU write 64: bit 24 clear 3541, flag 3541, I_STAT 3321
SPU write 16, I_STAT only: I_STAT 211
MDEC0 table 16: bit 24 clear 66, flag 66, I_STAT 66
MDEC1 block 16: bit 24 clear 833, flag 833, I_STAT 833
MDEC1 block 16, I_STAT only: I_STAT 876
OTC 16: bit 24 clear 67, flag 67, I_STAT 67
OTC 256: bit 24 clear 322, flag 322, I_STAT 322
OTC 16, I_STAT only: I_STAT 96
GPU write 16: bit 24 clear 78, flag 78, I_STAT 78
GPU write 64: bit 24 clear 136, flag 136, I_STAT 136
GPU write 16, I_STAT only: I_STAT 107
SPU write 16: bit 24 clear 180, flag 180, I_STAT 180
SPU write 64: bit 24 clear 3541, flag 3541, I_STAT 3321
SPU write 16, I_STAT only: I_STAT 211
MDEC0 table 16: bit 24 clear 66, flag 66, I_STAT 66
MDEC1 block 16: bit 24 clear 833, flag 833, I_STAT 833
MDEC1 block 16, I_STAT only: I_STAT 876
Done.