===== 05 DSP DMA SPU TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DMA4 to and from sound RAM at 1000h: clocks from the CHCR write to bit 24 clear (polls meanwhile), three times each; MADR, BCR, CHCR after. SPU delay was 200931E1, 220931E1 here.
Write SyncMode 1, 16 words x 1: 217 (1) 217 (1) 217 (1) | MADR start64, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 2: 1489 (89) 1288 (73) 1489 (89) | MADR start128, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 4: 3836 (249) 3840 (250) 3849 (250) | MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 8: 8547 (572) 8543 (572) 8547 (572) | MADR start512, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16: 17781 (1202) 17790 (1202) 17789 (1202) | MADR start1024, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 64: 73072 (4969) 73086 (4970) 73078 (4970) | MADR start4096, BCR 00000010, CHCR 00000201
Write SyncMode 1, 1 word x 64: 4089 (266) 4079 (265) 4088 (266) | MADR start256, BCR 00000001, CHCR 00000201
Write SyncMode 1, 2 words x 32: 4867 (330) 4895 (332) 4897 (332) | MADR start256, BCR 00000002, CHCR 00000201
Write SyncMode 1, 4 words x 16: 4487 (298) 4506 (300) 4493 (299) | MADR start256, BCR 00000004, CHCR 00000201
Write SyncMode 1, 8 words x 8: 4286 (284) 4491 (300) 4295 (285) | MADR start256, BCR 00000008, CHCR 00000201
Read SyncMode 1, 16 words x 1: 223 (1) 233 (2) 221 (1) | MADR start64, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 4: 3896 (254) 3566 (229) 3902 (255) | MADR start256, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16: 17378 (1170) 17802 (1203) 17825 (1205) | MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 64: 73084 (4970) 73119 (4973) 73109 (4972) | MADR start4096, BCR 00000010, CHCR 00000200
Read SyncMode 1, 4 words x 16: 4800 (325) 4795 (324) 4805 (326) | MADR start256, BCR 00000004, CHCR 00000200
Write SyncMode 0, 16 words: 219 (1) 222 (1) 222 (1) | MADR start0, BCR 00000010, CHCR 00000001
Write SyncMode 0, 64 words: 601 (1) 601 (1) 601 (1) | MADR start0, BCR 00000040, CHCR 00000001
Write SyncMode 0, 256 words: 2143 (1) 2141 (1) 2137 (1) | MADR start0, BCR 00000100, CHCR 00000001
Write SyncMode 0 bit 28, 64 words: 601 (1) 602 (1) 605 (1) | MADR start0, BCR 00000040, CHCR 00000001
Read SyncMode 0, 64 words: 634 (3) 644 (4) 644 (4) | MADR start0, BCR 00000040, CHCR 00000000
Read SyncMode 0 bit 28, 64 words: 613 (1) 613 (1) 614 (1) | MADR start0, BCR 00000040, CHCR 00000000
Write SyncMode 1 bit 28, 16 words x 4: 3846 (250) 3852 (250) 3849 (250) | MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16, SPU delay 220931F1: 17776 (1201) 17774 (1201) 17344 (1167) | MADR start1024, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 16, SPU delay 220931F1: 17805 (1203) 17797 (1202) 17809 (1204) | MADR start1024, BCR 00000010, CHCR 00000200
Write SyncMode 1, 16 words x 16, SPU delay 22093141: 17584 (1186) 17348 (1167) 17693 (1194) | MADR start1024, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 16, delay 200931E1: 16858 (1215) 16872 (1216) 16871 (1215) | MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16, delay 220931E1: 17814 (1204) 17813 (1204) 17825 (1205) | MADR start1024, BCR 00000010, CHCR 00000200
64 words written then read back, SyncMode 1: 55 of 64 match
64 words written then read back, SyncMode 0: 16 of 64 match
Done.