===== 15 SDS F2 DMA SPU COST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
DMA4 SPU write, SyncMode 1, to 30000h, delay register 1F801014h = 200931E1h (it was
200931E1). Cycles from the CHCR write until bit 24 clears, three times each.
Blocks of 1 words x 256 (256 words): 16396 16345 16348
Blocks of 2 words x 128 (256 words): 16293 16268 16298
Blocks of 3 words x 85 (255 words): 17625 17171 16204
Blocks of 4 words x 64 (256 words): 18048 18072 18072
Blocks of 5 words x 51 (255 words): 17596 17562 17576
Blocks of 6 words x 42 (252 words): 17022 17014 17014
Blocks of 8 words x 32 (256 words): 17043 17043 17043
Blocks of 12 words x 21 (252 words): 15829 15828 15828
Blocks of 16 words x 16 (256 words): 16873 16850 16849
Blocks of 24 words x 10 (240 words): 10411 10394 10394
Blocks of 31 words x 8 (248 words): 8103 8158 8117
Blocks of 32 words x 8 (256 words): 8169 8135 8162
SyncMode 0, which the CPU cannot poll during: not run in this table.
Done.