===== 07 FSP FU SPU ENV FIFO | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Envelope counter, one for all voices or one each: voices 0 and 1 attack linear shift
16 step 0, keyed on 1500 cycles apart; cycles from voice 0's KON.
Voice 0 keyed on at 0, voice 1 at 1646; first level changes, voice 0: 17918 42486 67054 91702; voice 1: 17918 42486 67054 91702; levels then 002A 002A
Voice 0 keyed on at 0, voice 1 at 1597; first level changes, voice 0: 17800 42352 66928 91576; voice 1: 17800 42352 66928 91576; levels then 002A 002A
Voice 0 keyed on at 0, voice 1 at 1597; first level changes, voice 0: 17889 42441 67000 91553; voice 1: 17889 42441 67000 91553; levels then 002A 002A
ADSR level times the sample: tone T on voice 1, pitch 1000h, held at 7FFFh; the level
register written, then the voice 1 capture buffer (first 16 samples).
Level as it stands, 255 changes in 256:
  014C 01B7 021B 0278 02D0 0322 036F 0392 02FE 024F 01AA 010F 007E FFF7 FF78 FF01
Level read 3FFF
Level written 4000h, reads 4000
Level 4000h, 255 changes in 256:
  02FF 024F 01AA 0110 007F FFF7 FF78 FF01 FE91 FE29 FDC7 FD6A FD14 FD4A FF98 007F
Level written 7FFFh, reads 7FFF
Level 7FFFh, 255 changes in 256:
  FD23 FC53 FB8E FAD5 FA29 FA94 FF31 00FD 01FC 02FB 03FA 04F9 05F8 0497 FA60 F907
FIFO drain: halfwords B000h, B001h, .. to scratch at 30000h (filled EEEEh) by one DMA
block of 16 words, a wait, SPUCNT transfer mode Stop, then read back by DMA.
Wait 0 cycles after the DMA ended: 9 of 32 halfwords written, 16 still EEEEh, first B000 last EEEE
Wait 100 cycles after the DMA ended: 10 of 32 halfwords written, 16 still EEEEh, first B000 last EEEE
Wait 200 cycles after the DMA ended: 10 of 32 halfwords written, 16 still EEEEh, first B000 last EEEE
Wait 300 cycles after the DMA ended: 14 of 32 halfwords written, 16 still EEEEh, first B000 last EEEE
Wait 400 cycles after the DMA ended: 18 of 32 halfwords written, 14 still EEEEh, first B000 last EEEE
Wait 500 cycles after the DMA ended: 22 of 32 halfwords written, 10 still EEEEh, first B000 last EEEE
Wait 600 cycles after the DMA ended: 26 of 32 halfwords written, 6 still EEEEh, first B000 last EEEE
Wait 700 cycles after the DMA ended: 31 of 32 halfwords written, 1 still EEEEh, first B000 last EEEE
Wait 800 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 900 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1000 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1100 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1200 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1300 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1400 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1500 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1600 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Start address one 8 byte unit past a block (spuenv END's S4+8 case): tone T on voice 1,
pitch 1000h, start and repeat as given; the voice 1 capture buffer.
Start 40C0h (the block), 65 changes in 256:
  0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
  0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Start 40C1h (one unit in), 255 changes in 256:
  FDC7 FD6A FD14 FD4A FF98 007E 00FE 017D 01FD 027C 02FC 024B FD30 FC83 FD03 FD82
  FE01 FE81 FF00 FF80 FFFF 007E 00FE 017D 01FD 027C 02FC 024B FD30 FC83 FD03 FD88
Done.