===== 05 ILT IRQ LATENCY POLLED | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Poll loop period, 1000 turns: 15020 cycles
Counter at the turn that saw the IRQ, minus the target (targets 300-307):
T2 sysclk, I_STAT.6: 11 5 4 3 2 1 15 14
T2 sysclk, CAUSE.IP2: 4 12 11 10 9 8 7 6
T2 sysclk/8, I_STAT.6 (in 8s): 1 1 1 0 1 1 0 0
T0 sysclk, I_STAT.4: 6 5 4 3 2 1 15 14
T1 sysclk, I_STAT.5: 6 5 4 3 2 1 15 14
T0 sysclk, CAUSE.IP2: 13 12 11 10 9 8 7 6
T1 sysclk reset at VBlank, value when I_STAT.0 seen: 43476 57859 57861 57866 57863 57869 57866 57857
T1 hblank reset at VBlank, value when I_STAT.0 seen: 237 237 237 237 237 237 237 237
T1 hblank free, hblanks between VBlank IRQs: 263 263 263 263
OTC  16 words: CHCR.24 clear at 55, I_STAT.3 at 55, DICR 31-24 C0
OTC  16 words: CHCR.24 clear at 41, I_STAT.3 at 41, DICR 31-24 C0
OTC  16 words: CHCR.24 clear at 31, I_STAT.3 at 31, DICR 31-24 C0
OTC  64 words: CHCR.24 clear at 11, I_STAT.3 at 11, DICR 31-24 C0
OTC  64 words: CHCR.24 clear at 79, I_STAT.3 at 79, DICR 31-24 C0
OTC  64 words: CHCR.24 clear at 79, I_STAT.3 at 79, DICR 31-24 C0
OTC 256 words: CHCR.24 clear at 286, I_STAT.3 at 286, DICR 31-24 C0
OTC 256 words: CHCR.24 clear at 286, I_STAT.3 at 286, DICR 31-24 C0
OTC 256 words: CHCR.24 clear at 286, I_STAT.3 at 286, DICR 31-24 C0
Done.