===== 11 TMR TIMERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A timers test Detected NTSC system. Forced NTSC system. Timer0, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer0, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer0, clock: System clock, frame delay: 106394, 107338, 107349, 107364, 107330, 107336, 107348, 107344, 107358, 107328, Timer0, clock: Dot clock, 1000 cycles delay: 199, 200, 200, 201, 200, 201, 200, 200, 200, 200, Timer0, clock: Dot clock, 5000 cycles delay: 991, 991, 992, 992, 992, 992, 992, 992, 991, 991, Timer0, clock: Dot clock, frame delay: 111934, 112031, 112037, 112029, 112030, 112033, 112032, 112038, 112028, 112033, Timer1, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer1, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer1, clock: System clock, frame delay: 106819, 107374, 107318, 107349, 107335, 107351, 107349, 107326, 107366, 107335, Timer1, clock: Hblank, 1000 cycles delay: 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, Timer1, clock: Hblank, 5000 cycles delay: 3, 2, 2, 3, 2, 2, 3, 2, 2, 3, Timer1, clock: Hblank, frame delay: 263, 263, 263, 263, 263, 263, 263, 263, 263, 263, Timer2, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer2, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer2, clock: System clock, frame delay: 106837, 107323, 107358, 107337, 107347, 107352, 107332, 107359, 107337, 107347, Timer2, clock: System clock/8, 1000 cycles delay: 126, 126, 127, 126, 127, 126, 126, 127, 126, 126, Timer2, clock: System clock/8, 5000 cycles delay: 626, 627, 626, 627, 626, 626, 627, 626, 626, 627, Timer2, clock: System clock/8, frame delay: 70701, 70759, 70762, 70764, 70759, 70763, 70759, 70764, 70760, 70761, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs) 0 = Pause counter during Hblanks 216, 338, 460, 582, 704, 826, 948, 1070, 1192, 1314, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs) 0 = Pause counter during Hblanks 275, 397, 519, 641, 763, 885, 974, 974, 974, 974, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 606, 42, 164, 286, 408, 530, 652, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 97, 219, 341, 463, 585, 707, 829, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs) 0 = Pause counter during Hblanks 0, 120, 242, 364, 486, 608, 730, 852, 974, 1096, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 111, 233, 355, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 60, 182, 304, 426, 548, 670, 792, 914, 1036, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs) 0 = Pause counter during Hblanks 282, 404, 468, 468, 468, 468, 476, 598, 720, 842, 1 = Reset counter to 0 at Hblanks 62, 184, 306, 428, 550, 672, 794, 916, 1038, 1160, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 254, 376, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 44, 166, 288, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs) 0 = Pause counter during Hblanks 282, 404, 526, 648, 660, 660, 660, 660, 719, 841, 1 = Reset counter to 0 at Hblanks 240, 2, 124, 246, 368, 490, 612, 734, 856, 978, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 67, 189, 311, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 97, 219, 341, 463, 585, 707, 829, 951, 1073, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs) 0 = Pause counter during Hblanks 45, 64, 84, 103, 122, 142, 161, 180, 200, 219, 1 = Reset counter to 0 at Hblanks 38, 57, 76, 95, 4, 23, 42, 62, 81, 101, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 15, 34, 53, 72, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs) 0 = Pause counter during Hblanks 55, 79, 103, 127, 151, 175, 200, 224, 248, 272, 1 = Reset counter to 0 at Hblanks 47, 71, 95, 119, 143, 6, 30, 54, 78, 102, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 17, 40, 64, 89, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs) 0 = Pause counter during Hblanks 62, 89, 117, 145, 172, 200, 228, 255, 283, 310, 1 = Reset counter to 0 at Hblanks 57, 85, 113, 140, 168, 196, 223, 251, 278, 306, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 36, 63, 91, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 24, 51, 79, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs) 0 = Pause counter during Hblanks 89, 128, 166, 205, 244, 282, 321, 333, 333, 333, 1 = Reset counter to 0 at Hblanks 75, 114, 152, 191, 37, 75, 114, 153, 191, 230, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 7, 45, 84, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs) 0 = Pause counter during Hblanks 81, 81, 81, 81, 94, 142, 190, 239, 287, 335, 1 = Reset counter to 0 at Hblanks 95, 143, 191, 240, 288, 336, 3, 51, 99, 148, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 13, 61, 109, 3 = Pause until Hblank occurs once, then switch to Free Run 48, 97, 145, 193, 242, 290, 338, 387, 435, 483, Testing Timer1 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Pause counter during Vblanks 270, 392, 514, 636, 758, 880, 1002, 1124, 1246, 1368, 1 = Reset counter to 0 at Vblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Vblanks and pause outside of Vblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Vblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer1 sync modes (clock source = Hblank, 100 delay cycles, not resetted between runs) 0 = Pause counter during Vblanks 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 = Reset counter to 0 at Vblanks 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2 = Reset counter to 0 at Vblanks and pause outside of Vblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Vblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 = Free Run 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Free Run 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 3 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 = Free Run 239, 361, 483, 605, 727, 849, 971, 1093, 1215, 1337, 2 = Free Run 239, 361, 483, 605, 727, 849, 971, 1093, 1215, 1337, 3 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Check when Timer2 counter (System clock) is reset when reaching target (= 10). counter == 0, 1667 ticks counter == 1, 833 ticks counter == 2, 831 ticks counter == 3, 837 ticks counter == 4, 833 ticks counter == 5, 831 ticks counter == 6, 836 ticks counter == 7, 832 ticks counter == 8, 831 ticks counter == 9, 836 ticks counter == 10, 833 ticks <<<< This value should be non-zero counter == 11, 0 ticks Reached target: 1 (ok) Reached 0xFFFF: 0 (ok) Counter reset AFTER reaching target: 1 (ok) Target + 1 not reached: 1 (ok) Check if write to mode register acknowledges the targetReached flag Write 0x0000 to Timer0.mode, read 0x0400 Write 0xffff to Timer0.mode, read 0x07ff Read mode after waiting for targetReached: 0x1c08 Read again: 0x0408 Write mode after waiting for targetReached and then read: 0x1c08 Read again: 0x0408 Done.