===== 04 SRT SPU READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A BadVaddr as the group starts: 00000480 SPU reads at 1F801C00, SPU delay 200931E1: SPU lw, read delay 0: 1444, value FFFFFFFF SPU lw, read delay 1: 1641, value FFFFFFFF SPU lw, read delay 2: 1841, value FFFFFFFF SPU lw, read delay 3: 2044, value FFFFFFFF SPU lw, read delay 4: 2241, value FFFFFFFF SPU lw, read delay 5: 2441, value FFFFFFFF SPU lw, read delay 6: 2641, value FFFFFFFF SPU lw, read delay 7: 2844, value FFFFFFFF SPU lw, read delay 8: 3044, value FFFFFFFF SPU lw, read delay 9: 3241, value FFFFFFFF SPU lw, read delay 10: 3441, value FFFFFFFF SPU lw, read delay 11: 3654, value 00000000 SPU lw, read delay 12: 3841, value 00000000 SPU lw, read delay 13: 4047, value 00000000 SPU lw, read delay 14: 4245, value 00000000 SPU lw, read delay 15: 4447, value 00000000 SPU lhu, read delay 0: 852, value 0000FFFF SPU lhu, read delay 1: 952, value 0000FFFF SPU lhu, read delay 2: 1052, value 0000FFFF SPU lhu, read delay 3: 1152, value 0000FFFF SPU lhu, read delay 4: 1252, value 0000FFFF SPU lhu, read delay 5: 1358, value 0000FFFF SPU lhu, read delay 6: 1452, value 0000FFFF SPU lhu, read delay 7: 1557, value 0000FFFF SPU lhu, read delay 8: 1652, value 0000FFFF SPU lhu, read delay 9: 1752, value 0000FFFF SPU lhu, read delay 10: 1853, value 0000FFFF SPU lhu, read delay 11: 1952, value 00000000 SPU lhu, read delay 12: 2052, value 00000000 SPU lhu, read delay 13: 2152, value 00000000 SPU lhu, read delay 14: 2252, value 00000000 SPU lhu, read delay 15: 2352, value 00000000 SPU lbu, read delay 0: 844, value 000000FF SPU lbu, read delay 1: 945, value 000000FF SPU lbu, read delay 2: 1041, value 000000FF SPU lbu, read delay 3: 1141, value 000000FF SPU lbu, read delay 4: 1241, value 000000FF SPU lbu, read delay 5: 1341, value 000000FF SPU lbu, read delay 6: 1441, value 000000FF SPU lbu, read delay 7: 1541, value 000000FF SPU lbu, read delay 8: 1641, value 000000FF SPU lbu, read delay 9: 1741, value 000000FF SPU lbu, read delay 10: 1846, value 000000FF SPU lbu, read delay 11: 1941, value 00000000 SPU lbu, read delay 12: 2044, value 00000000 SPU lbu, read delay 13: 2146, value 00000000 SPU lbu, read delay 14: 2241, value 00000000 SPU lbu, read delay 15: 2341, value 00000000 SPU lw, as set (200931E1): 4248, value 00000000 SPU lhu, as set (200931E1): 2252, value 00000000 SPU lbu, as set (200931E1): 2241, value 00000000 SPU lw, bit 8 flipped (200930E1): 3844, value 00000000 SPU lhu, bit 8 flipped (200930E1): 2252, value 00000000 SPU lbu, bit 8 flipped (200930E1): 2241, value 00000000 SPU lw, bit 9 flipped (200933E1): 4244, value 00000000 SPU lhu, bit 9 flipped (200933E1): 2252, value 00000000 SPU lbu, bit 9 flipped (200933E1): 2241, value 00000000 SPU lw, bit 10 flipped (200935E1): 4444, value 00000000 SPU lhu, bit 10 flipped (200935E1): 2257, value 00000000 SPU lbu, bit 10 flipped (200935E1): 2241, value 00000000 SPU lw, bit 11 flipped (200939E1): 4244, value 00000000 SPU lhu, bit 11 flipped (200939E1): 2252, value 00000000 SPU lbu, bit 11 flipped (200939E1): 2241, value 00000000 SPU lw, bit 12 flipped (200921E1): 8244, value 00000000 SPU lhu, bit 12 flipped (200921E1): 4252, value 00000000 SPU lbu, bit 12 flipped (200921E1): 2244, value 00000000 SPU lw, bit 13 flipped (200911E1): 4244, value 00000000 SPU lhu, bit 13 flipped (200911E1): 2252, value 00000000 SPU lbu, bit 13 flipped (200911E1): 2244, value 00000000 SPU lw, bit 29 flipped (000931E1): 4244, value 00000000 SPU lhu, bit 29 flipped (000931E1): 2252, value 00000000 SPU lbu, bit 29 flipped (000931E1): 2241, value 00000000 SPU lhu, bits 24-27 = F: 2252, value 00000000 SPU lhu, bits 24-27 = 2 (220931E1h): 2257, value 00000000 Done.