===== 05 DSP DMA SPU TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
DMA4 to and from sound RAM at 1000h: clocks from the CHCR write to bit 24 clear (polls meanwhile), three times each; MADR, BCR, CHCR after. SPU delay was 200931E1, 220931E1 here.
Write SyncMode 1, 16 words x 1: 221 (1) 217 (1) 217 (1) | MADR start64, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 2: 1493 (89) 1481 (88) 1285 (73) | MADR start128, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 4: 3841 (250) 3518 (225) 3829 (249) | MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 8: 8543 (572) 8545 (572) 8124 (539) | MADR start512, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16: 17767 (1200) 17779 (1201) 17773 (1201) | MADR start1024, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 64: 73069 (4969) 73075 (4969) 73069 (4969) | MADR start4096, BCR 00000010, CHCR 00000201
Write SyncMode 1, 1 word x 64: 4082 (265) 4077 (264) 4073 (264) | MADR start256, BCR 00000001, CHCR 00000201
Write SyncMode 1, 2 words x 32: 4863 (330) 4883 (331) 4897 (332) | MADR start256, BCR 00000002, CHCR 00000201
Write SyncMode 1, 4 words x 16: 4515 (301) 4490 (299) 4505 (300) | MADR start256, BCR 00000004, CHCR 00000201
Write SyncMode 1, 8 words x 8: 4476 (299) 4277 (284) 4299 (285) | MADR start256, BCR 00000008, CHCR 00000201
Read SyncMode 1, 16 words x 1: 220 (1) 227 (2) 227 (2) | MADR start64, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 4: 3555 (228) 3565 (229) 3928 (257) | MADR start256, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16: 17378 (1170) 17806 (1204) 17792 (1202) | MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 64: 73081 (4970) 73094 (4971) 73088 (4970) | MADR start4096, BCR 00000010, CHCR 00000200
Read SyncMode 1, 4 words x 16: 4799 (325) 4797 (325) 4811 (326) | MADR start256, BCR 00000004, CHCR 00000200
Write SyncMode 0, 16 words: 217 (1) 217 (1) 219 (1) | MADR start0, BCR 00000010, CHCR 00000001
Write SyncMode 0, 64 words: 601 (1) 603 (1) 601 (1) | MADR start0, BCR 00000040, CHCR 00000001
Write SyncMode 0, 256 words: 2141 (1) 2137 (1) 2141 (1) | MADR start0, BCR 00000100, CHCR 00000001
Write SyncMode 0 bit 28, 64 words: 605 (1) 601 (1) 601 (1) | MADR start0, BCR 00000040, CHCR 00000001
Read SyncMode 0, 64 words: 626 (2) 649 (4) 629 (3) | MADR start0, BCR 00000040, CHCR 00000000
Read SyncMode 0 bit 28, 64 words: 615 (1) 613 (1) 612 (1) | MADR start0, BCR 00000040, CHCR 00000000
Write SyncMode 1 bit 28, 16 words x 4: 3840 (250) 3518 (225) 3829 (249) | MADR start256, BCR 00000010, CHCR 00000201
Write SyncMode 1, 16 words x 16, SPU delay 220931F1: 17782 (1202) 17341 (1167) 17773 (1201) | MADR start1024, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 16, SPU delay 220931F1: 17807 (1204) 17389 (1171) 17804 (1204) | MADR start1024, BCR 00000010, CHCR 00000200
Write SyncMode 1, 16 words x 16, SPU delay 22093141: 17598 (1188) 17363 (1169) 17687 (1194) | MADR start1024, BCR 00000010, CHCR 00000201
Read SyncMode 1, 16 words x 16, delay 200931E1: 16867 (1215) 16873 (1215) 16887 (1216) | MADR start1024, BCR 00000010, CHCR 00000200
Read SyncMode 1, 16 words x 16, delay 220931E1: 17375 (1170) 17806 (1204) 17792 (1202) | MADR start1024, BCR 00000010, CHCR 00000200
64 words written then read back, SyncMode 1: 56 of 64 match
64 words written then read back, SyncMode 0: 16 of 64 match
Done.