===== 15 SDS F2 DMA SPU COST | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
DMA4 SPU write, SyncMode 1, to 30000h, delay register 1F801014h = 200931E1h (it was
200931E1). Cycles from the CHCR write until bit 24 clears, three times each.
Blocks of 1 words x 256 (256 words): 16345 16335 16334
Blocks of 2 words x 128 (256 words): 16297 16297 16297
Blocks of 3 words x 85 (255 words): 17188 17181 17181
Blocks of 4 words x 64 (256 words): 18079 18063 18063
Blocks of 5 words x 51 (255 words): 17611 17573 17595
Blocks of 6 words x 42 (252 words): 17004 17010 17010
Blocks of 8 words x 32 (256 words): 17042 17066 17066
Blocks of 12 words x 21 (252 words): 15825 15799 15837
Blocks of 16 words x 16 (256 words): 16864 16861 16862
Blocks of 24 words x 10 (240 words): 10374 10374 10374
Blocks of 31 words x 8 (248 words): 8137 8143 8143
Blocks of 32 words x 8 (256 words): 8138 8138 8138
SyncMode 0, which the CPU cannot poll during: not run in this table.
Done.