===== 01 FMR FU MDEC DMA RESET | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
MDEC by DMA after a reset, then a CPU store to a full input FIFO. Each step saves the
log first.
One decode by DMA, the reset writes, then DMA0 alone: not run in this table.
A 33rd input word with bit 30 set:
  32 words written while bit 30 was clear, status E60400DF; the next word's store between timer 2 7 and 28; status then E60400DF; 0 words read out after, last 00000000, status E60400DF
Done.