===== 07 FSP FU SPU ENV FIFO | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Envelope counter, one for all voices or one each: voices 0 and 1 attack linear shift
16 step 0, keyed on 1500 cycles apart; cycles from voice 0's KON.
Voice 0 keyed on at 0, voice 1 at 1636; first level changes, voice 0: 24084 48652 73220 97764; voice 1: 24084 48652 73220 97764; levels then 002A 002A
Voice 0 keyed on at 0, voice 1 at 1605; first level changes, voice 0: 17803 42355 66923 91563; voice 1: 17803 42355 66923 91563; levels then 002A 002A
Voice 0 keyed on at 0, voice 1 at 1568; first level changes, voice 0: 17864 42408 66976 91528; voice 1: 17864 42408 66976 91528; levels then 002A 002A
ADSR level times the sample: tone T on voice 1, pitch 1000h, held at 7FFFh; the level
register written, then the voice 1 capture buffer (first 16 samples).
Level as it stands, 255 changes in 256:
  FC83 FD03 FD88 FE28 FEC5 FF57 FFE1 0062 00DB 014C 01B7 021B 0278 02D0 0322 036F
Level read 3FFF
Level written 4000h, reads 4000
Level 4000h, 255 changes in 256:
  00DB 014D 01B7 021B 0279 02D1 0323 0370 0392 02FF 024F 01AA 0110 007F FFF7 FF78
Level written 7FFFh, reads 7FFF
Level 7FFFh, 255 changes in 256:
  0724 05FD 049E 0354 021F 00FD FFEF FEF1 FE03 FD23 FC53 FB8E FAD5 FA29 FA94 FF31
FIFO drain: halfwords B000h, B001h, .. to scratch at 30000h (filled EEEEh) by one DMA
block of 16 words, a wait, SPUCNT transfer mode Stop, then read back by DMA.
Wait 0 cycles after the DMA ended: 9 of 32 halfwords written, 16 still EEEEh, first B000 last EEEE
Wait 100 cycles after the DMA ended: 9 of 32 halfwords written, 16 still EEEEh, first B000 last EEEE
Wait 200 cycles after the DMA ended: 10 of 32 halfwords written, 16 still EEEEh, first B000 last EEEE
Wait 300 cycles after the DMA ended: 15 of 32 halfwords written, 16 still EEEEh, first B000 last EEEE
Wait 400 cycles after the DMA ended: 19 of 32 halfwords written, 13 still EEEEh, first B000 last EEEE
Wait 500 cycles after the DMA ended: 23 of 32 halfwords written, 9 still EEEEh, first B000 last EEEE
Wait 600 cycles after the DMA ended: 27 of 32 halfwords written, 5 still EEEEh, first B000 last EEEE
Wait 700 cycles after the DMA ended: 31 of 32 halfwords written, 1 still EEEEh, first B000 last EEEE
Wait 800 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 900 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1000 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1100 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1200 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1300 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1400 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1500 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1600 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Start address one 8 byte unit past a block (spuenv END's S4+8 case): tone T on voice 1,
pitch 1000h, start and repeat as given; the voice 1 capture buffer.
Start 40C0h (the block), 64 changes in 256:
  0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
  0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Start 40C1h (one unit in), 255 changes in 256:
  FE29 FDC7 FD6A FD14 FD4A FF98 007E 00FE 017D 01FD 027C 02FC 024B FD30 FC83 FD03
  FD82 FE01 FE81 FF00 FF80 FFFF 007E 00FE 017D 01FD 027C 02FC 024B FD30 FC83 FD03
Done.