===== 11 TMR TIMERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A timers test Detected NTSC system. Forced NTSC system. Timer0, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer0, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer0, clock: System clock, frame delay: 106416, 107338, 107338, 107375, 107330, 107336, 107338, 107349, 107364, 107330, Timer0, clock: Dot clock, 1000 cycles delay: 200, 200, 200, 200, 199, 200, 200, 201, 200, 201, Timer0, clock: Dot clock, 5000 cycles delay: 992, 992, 991, 991, 992, 992, 991, 992, 992, 991, Timer0, clock: Dot clock, frame delay: 111934, 112033, 112035, 112030, 112031, 112033, 112033, 112035, 112030, 112030, Timer1, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer1, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer1, clock: System clock, frame delay: 106828, 107364, 107330, 107336, 107348, 107344, 107358, 107331, 107336, 107348, Timer1, clock: Hblank, 1000 cycles delay: 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, Timer1, clock: Hblank, 5000 cycles delay: 3, 2, 2, 3, 2, 2, 3, 2, 2, 3, Timer1, clock: Hblank, frame delay: 263, 263, 263, 263, 263, 263, 263, 263, 263, 263, Timer2, clock: System clock, 1000 cycles delay: 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, 1011, Timer2, clock: System clock, 5000 cycles delay: 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, 5011, Timer2, clock: System clock, frame delay: 106823, 107332, 107349, 107339, 107363, 107328, 107332, 107349, 107339, 107363, Timer2, clock: System clock/8, 1000 cycles delay: 126, 126, 127, 126, 127, 126, 126, 127, 126, 126, Timer2, clock: System clock/8, 5000 cycles delay: 626, 627, 626, 627, 626, 626, 627, 626, 626, 627, Timer2, clock: System clock/8, frame delay: 70698, 70762, 70760, 70765, 70758, 70762, 70760, 70760, 70765, 70758, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs) 0 = Pause counter during Hblanks 148, 270, 392, 514, 636, 758, 880, 1002, 1124, 1246, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs) 0 = Pause counter during Hblanks 275, 397, 519, 641, 763, 885, 984, 984, 984, 984, 1 = Reset counter to 0 at Hblanks 240, 362, 484, 606, 3, 125, 247, 369, 491, 613, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 63, 185, 307, 429, 551, 673, 795, 917, 1039, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs) 0 = Pause counter during Hblanks 270, 392, 505, 505, 505, 505, 544, 666, 788, 910, 1 = Reset counter to 0 at Hblanks 86, 208, 330, 452, 574, 696, 818, 940, 1062, 1184, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs) 0 = Pause counter during Hblanks 282, 404, 526, 648, 656, 656, 656, 656, 719, 841, 1 = Reset counter to 0 at Hblanks 240, 362, 117, 239, 361, 483, 605, 727, 849, 971, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 254, 376, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 117, 239, Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs) 0 = Pause counter during Hblanks 282, 404, 496, 496, 496, 496, 496, 597, 719, 841, 1 = Reset counter to 0 at Hblanks 240, 111, 233, 355, 477, 599, 721, 843, 965, 1087, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs) 0 = Pause counter during Hblanks 6, 25, 45, 64, 83, 103, 122, 141, 161, 180, 1 = Reset counter to 0 at Hblanks 40, 59, 79, 98, 117, 137, 156, 175, 4, 23, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 19, 38, 57, 77, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs) 0 = Pause counter during Hblanks 25, 49, 73, 97, 121, 145, 170, 194, 218, 242, 1 = Reset counter to 0 at Hblanks 48, 71, 95, 120, 5, 29, 53, 77, 101, 126, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 7, 31, 55, 79, 103, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs) 0 = Pause counter during Hblanks 61, 89, 116, 144, 172, 199, 227, 255, 282, 310, 1 = Reset counter to 0 at Hblanks 57, 85, 112, 140, 168, 195, 223, 250, 278, 305, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 54, 81, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 8, 35, 63, 90, 118, 146, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs) 0 = Pause counter during Hblanks 89, 128, 166, 205, 244, 282, 321, 360, 399, 437, 1 = Reset counter to 0 at Hblanks 76, 115, 153, 192, 230, 269, 308, 346, 37, 76, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs) 0 = Pause counter during Hblanks 80, 80, 80, 80, 92, 140, 188, 237, 285, 333, 1 = Reset counter to 0 at Hblanks 95, 143, 192, 240, 288, 337, 385, 30, 79, 127, 2 = Reset counter to 0 at Hblanks and pause outside of Hblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Hblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer1 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Pause counter during Vblanks 270, 392, 514, 636, 758, 880, 1002, 1124, 1246, 1368, 1 = Reset counter to 0 at Vblanks 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Reset counter to 0 at Vblanks and pause outside of Vblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Vblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer1 sync modes (clock source = Hblank, 100 delay cycles, not resetted between runs) 0 = Pause counter during Vblanks 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 = Reset counter to 0 at Vblanks 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2 = Reset counter to 0 at Vblanks and pause outside of Vblank 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 = Pause until Vblank occurs once, then switch to Free Run 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 = Free Run 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 2 = Free Run 240, 362, 484, 606, 728, 850, 972, 1094, 1216, 1338, 3 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs) 0 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 = Free Run 239, 361, 483, 605, 727, 849, 971, 1093, 1215, 1337, 2 = Free Run 239, 361, 483, 605, 727, 849, 971, 1093, 1215, 1337, 3 = Stop counter at current value 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Check when Timer2 counter (System clock) is reset when reaching target (= 10). counter == 0, 1665 ticks counter == 1, 834 ticks counter == 2, 831 ticks counter == 3, 835 ticks counter == 4, 834 ticks counter == 5, 832 ticks counter == 6, 834 ticks counter == 7, 834 ticks counter == 8, 832 ticks counter == 9, 834 ticks counter == 10, 835 ticks <<<< This value should be non-zero counter == 11, 0 ticks Reached target: 1 (ok) Reached 0xFFFF: 0 (ok) Counter reset AFTER reaching target: 1 (ok) Target + 1 not reached: 1 (ok) Check if write to mode register acknowledges the targetReached flag Write 0x0000 to Timer0.mode, read 0x0400 Write 0xffff to Timer0.mode, read 0x07ff Read mode after waiting for targetReached: 0x1c08 Read again: 0x0408 Write mode after waiting for targetReached and then read: 0x1c08 Read again: 0x0408 Done.