===== 10 MTM M2 DECODE TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
Decodes by DMA0 (blocks of 32) and DMA1 (blocks of 32, or the whole output when
smaller), DMA1 armed first. Cycles (timer / 8, times 8) from the DMA0 start to DMA0
done and to DMA1 done. DC-only blocks unless dense (63 AC of +-3, run 0).
15 bit, 1 macroblocks: 32 words in, 128 out: DMA0 done 2912, DMA1 done 5152, status E0041CDC
15 bit, 2 macroblocks: 32 words in, 256 out: DMA0 done 2912, DMA1 done 10000088 (timed out), status 30041CDC
15 bit, 4 macroblocks: 32 words in, 512 out: DMA0 done 2912, DMA1 done 10000104 (timed out), status 30041CDC
15 bit, 8 macroblocks: 64 words in, 1024 out: DMA0 done 19104, DMA1 done 10000088 (timed out), status 30041CBC
15 bit, 16 macroblocks: 96 words in, 2048 out: DMA0 done 35504, DMA1 done 10000072 (timed out), status 30041C9C
24 bit, 1 macroblocks: 32 words in, 192 out: DMA0 done 2920, DMA1 done 10000088 (timed out), status 30041CDC
24 bit, 2 macroblocks: 32 words in, 384 out: DMA0 done 2912, DMA1 done 10000104 (timed out), status 30041CDC
24 bit, 4 macroblocks: 32 words in, 768 out: DMA0 done 2920, DMA1 done 10000104 (timed out), status 30041CDC
24 bit, 8 macroblocks: 64 words in, 1536 out: DMA0 done 19096, DMA1 done 10000072 (timed out), status 30041CBC
24 bit, 16 macroblocks: 96 words in, 3072 out: DMA0 done 35408, DMA1 done 10000088 (timed out), status 30041C9C
8 bit, 1 blocks: 32 words in, 16 out: DMA0 done 4294967295, DMA1 done 168, status 68041CFC
8 bit, 4 blocks: 32 words in, 64 out: DMA0 done 4294967295, DMA1 done 1056, status E0041CFC
8 bit, 16 blocks: 32 words in, 256 out: DMA0 done 2928, DMA1 done 10000080 (timed out), status 30041CDC
8 bit, 64 blocks: 64 words in, 1024 out: DMA0 done 19064, DMA1 done 10000104 (timed out), status 30041CBC
4 bit, 1 blocks: 32 words in, 8 out: DMA0 done 4294967295, DMA1 done 200, status 68041CFC
4 bit, 4 blocks: 32 words in, 32 out: DMA0 done 4294967295, DMA1 done 192, status 60041CFC
4 bit, 16 blocks: 32 words in, 128 out: DMA0 done 2944, DMA1 done 5168, status E0041CDC
4 bit, 64 blocks: 64 words in, 512 out: DMA0 done 19032, DMA1 done 29712, status E0041CBC
15 bit, 4 macroblocks, dense: 800 words in, 512 out: DMA0 done 15376, DMA1 done 10000072 (timed out), status 300419DC
24 bit, 4 macroblocks, dense: 800 words in, 768 out: DMA0 done 15432, DMA1 done 10000112 (timed out), status 300419DC
8 bit, 16 blocks, dense: 544 words in, 256 out: DMA0 done 11328, DMA1 done 10000088 (timed out), status 30041ADC
By CPU, three times each:
 15 bit macroblock: first output word ready 120 cycles after the last input word (52 to read the timer)
 24 bit macroblock: first output word ready 82 cycles after the last input word (22 to read the timer)
 8 bit block: first output word ready 82 cycles after the last input word (22 to read the timer)
 4 bit block: first output word ready 86 cycles after the last input word (22 to read the timer)
 15 bit macroblock: first output word ready 82 cycles after the last input word (22 to read the timer)
 24 bit macroblock: first output word ready 82 cycles after the last input word (22 to read the timer)
 8 bit block: first output word ready 82 cycles after the last input word (22 to read the timer)
 4 bit block: first output word ready 82 cycles after the last input word (27 to read the timer)
 15 bit macroblock: first output word ready 82 cycles after the last input word (22 to read the timer)
 24 bit macroblock: first output word ready 82 cycles after the last input word (22 to read the timer)
 8 bit block: first output word ready 84 cycles after the last input word (22 to read the timer)
 4 bit block: first output word ready 82 cycles after the last input word (22 to read the timer)
Done.