===== 01 SCN S2 SPUCNT BITS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
SPUCNT written from 8000h to each value, read back at once and after 3000 cycles,
with SPUSTAT beside it (nc control-and-status-register.txt:4-42). Main volume 0.
SPUCNT 8001: SPUCNT reads 8001 then 8001, SPUSTAT 0000 then 0001
SPUCNT 8002: SPUCNT reads 8002 then 8002, SPUSTAT 0000 then 0002
SPUCNT 8004: SPUCNT reads 8004 then 8004, SPUSTAT 0800 then 0804
SPUCNT 8008: SPUCNT reads 8008 then 8008, SPUSTAT 0800 then 0808
SPUCNT 8010: SPUCNT reads 8010 then 8010, SPUSTAT 0800 then 0810
SPUCNT 8020: SPUCNT reads 8020 then 8020, SPUSTAT 0800 then 0AA0
SPUCNT 8040: SPUCNT reads 8040 then 8040, SPUSTAT 0800 then 0800
SPUCNT 8080: SPUCNT reads 8080 then 8080, SPUSTAT 0800 then 0800
SPUCNT 8100: SPUCNT reads 8100 then 8100, SPUSTAT 0000 then 0000
SPUCNT 8200: SPUCNT reads 8200 then 8200, SPUSTAT 0000 then 0000
SPUCNT 8400: SPUCNT reads 8400 then 8400, SPUSTAT 0000 then 0000
SPUCNT 8800: SPUCNT reads 8800 then 8800, SPUSTAT 0000 then 0000
SPUCNT 9000: SPUCNT reads 9000 then 9000, SPUSTAT 0000 then 0000
SPUCNT A000: SPUCNT reads A000 then A000, SPUSTAT 0800 then 0800
SPUCNT C000: SPUCNT reads C000 then C000, SPUSTAT 0800 then 0800
SPUCNT 8000: SPUCNT reads 8000 then 8000, SPUSTAT 0800 then 0800
SPUCNT 0000: SPUCNT reads 0000 then 0000, SPUSTAT 0800 then 0800
Each transfer mode with the DMA4 enable in DPCR off and on, CHCR 0. SPUSTAT read
four times 500 cycles apart, from 2000 cycles after the mode is set:
Mode 0, DPCR enable 0: 0000 0000 0000 0000
Mode 0, DPCR enable 1: 0000 0000 0000 0000
Mode 1, DPCR enable 0: 0010 0010 0010 0010
Mode 1, DPCR enable 1: 0010 0010 0010 0010
Mode 2, DPCR enable 0: 02A0 02A0 02A0 02A0
Mode 2, DPCR enable 1: 02A0 02A0 02A0 02A0
Mode 3, DPCR enable 0: 01B0 01B0 01B0 01B0
Mode 3, DPCR enable 1: 09B0 09B0 09B0 09B0
lw of 1F801DACh reads 08000004 (transfer control 0004, SPUSTAT 0800)
lw of 1F801DA4h (IRQ address, transfer address) reads 60007FF0
Done.