===== 04 T0S T3 TIMER0 SOURCES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
GPUSTAT 5606200F
Timer 0, sources 1, 2, 3 (1 and 3 dotclock, 2 system clock), target 0040h, 140000 cycles. Each row: the mode written (bits 3-7 as in timers.txt:26-30), the
first read of the mode after the write, I_STAT bit 4 edges and their times, mode bit
10 changes (time:value), how many mode reads saw bits 11 and 12, and the counter and
mode at the end. Times are system clocks from the mode write.
T0 mode 0100 target 0040: first read 1D00; IRQ 0; bit 10 changes 0; 11 seen 1, 12 seen 0; end D8C4 0500
T0 mode 0108 target 0040: first read 1D08; IRQ 0; bit 10 changes 0; 11 seen 853, 12 seen 0; end 003B 0D08
T0 mode 0118 target 0040: first read 0D18; IRQ 1 at 196; bit 10 changes 0; 11 seen 853, 12 seen 0; end 002F 0D18
T0 mode 0158 target 0040: first read 0D58; IRQ 853 at 209 395 505 678; bit 10 changes 84 at 678:0 861:1 4946:0 5091:1; 11 seen 853, 12 seen 0; end 0013 0D58
T0 mode 01D8 target 0040: first read 0DD8; IRQ 427 at 72 177 521 861; bit 10 changes 852 at 273:0 395:1 521:0 739:1; 11 seen 852, 12 seen 0; end 003F 09D8
T0 mode 0160 target 0040: first read 0D60; IRQ 1 at 90; bit 10 changes 0; 11 seen 1, 12 seen 0; end D8BC 0560
T0 mode 0138 target 0040: first read 1D38; IRQ 1 at 209; bit 10 changes 0; 11 seen 853, 12 seen 0; end 0035 0D38
T0 mode 01F8 target 0040: first read 0DF8; IRQ 426 at 209 518 861 1161; bit 10 changes 852 at 209:0 396:1 518:0 739:1; 11 seen 853, 12 seen 0; end 0036 09F8
T0 mode 0200 target 0040: first read 0E00; IRQ 0; bit 10 changes 0; 11 seen 3, 12 seen 2; end 2320 0600
T0 mode 0208 target 0040: first read 0608; IRQ 0; bit 10 changes 0; 11 seen 1804, 12 seen 0; end 0009 0E08
T0 mode 0218 target 0040: first read 0E18; IRQ 1 at 143; bit 10 changes 0; 11 seen 1803, 12 seen 0; end 002F 0E18
T0 mode 0258 target 0040: first read 0E58; IRQ 1357 at 90 327 479 589; bit 10 changes 68 at 90:0 327:1 8351:0 8496:1; 11 seen 1357, 12 seen 0; end 0022 0E58
T0 mode 02D8 target 0040: first read 0ED8; IRQ 1060 at 72 254 483 636; bit 10 changes 541 at 254:0 483:1 636:0 991:1; 11 seen 1330, 12 seen 0; end 0000 0AD8
T0 mode 0260 target 0040: first read 0E60; IRQ 3 at 77 65582 131076; bit 10 changes 0; 11 seen 3, 12 seen 2; end 230A 0660
T0 mode 0238 target 0040: first read 1E38; IRQ 1 at 89; bit 10 changes 0; 11 seen 1804, 12 seen 0; end 0028 0E38
T0 mode 02F8 target 0040: first read 0EF8; IRQ 1055 at 143 331 483 667; bit 10 changes 543 at 143:0 331:1 667:0 825:1; 11 seen 1330, 12 seen 0; end 0006 0AF8
T0 mode 0300 target 0040: first read 0F00; IRQ 1 at 85; bit 10 changes 0; 11 seen 1, 12 seen 0; end D8D5 0700
T0 mode 0308 target 0040: first read 1F08; IRQ 0; bit 10 changes 0; 11 seen 852, 12 seen 0; end 002D 0F08
T0 mode 0318 target 0040: first read 0F18; IRQ 1 at 209; bit 10 changes 0; 11 seen 852, 12 seen 0; end 0008 0F18
T0 mode 0358 target 0040: first read 0F58; IRQ 852 at 201 400 573 680; bit 10 changes 68 at 1019:0 1185:1 6937:0 7082:1; 11 seen 853, 12 seen 0; end 003F 0F58
T0 mode 03D8 target 0040: first read 0FD8; IRQ 427 at 72 177 528 868; bit 10 changes 852 at 279:0 401:1 528:0 757:1; 11 seen 852, 12 seen 0; end 003F 0BD8
T0 mode 0360 target 0040: first read 0F60; IRQ 0; bit 10 changes 0; 11 seen 1, 12 seen 0; end D8C6 0760
T0 mode 0338 target 0040: first read 1F38; IRQ 1 at 202; bit 10 changes 0; 11 seen 853, 12 seen 0; end 003F 0F38
T0 mode 03F8 target 0040: first read 0FF8; IRQ 426 at 213 517 859 1219; bit 10 changes 852 at 213:0 395:1 615:0 737:1; 11 seen 852, 12 seen 0; end 0036 0BF8
Dotclock (source 1) at each display width, reset, IRQ at target 0100h, repeat:
Width 256, GPUSTAT 5600200F. T0 mode 0158 target 0100: first read 0D58; IRQ 37 at 1667 3269 4902 6531; bit 10 changes 0; 11 seen 39, 12 seen 0; end 0025 0558
Width 320, GPUSTAT 5602200F. T0 mode 0158 target 0100: first read 0D58; IRQ 46 at 1331 2657 3956 5267; bit 10 changes 8 at 18215:0 18389:1 40289:0 40434:1; 11 seen 47, 12 seen 0; end 003C 0558
Width 368, GPUSTAT D601200F. T0 mode 0158 target 0100: first read 0D58; IRQ 52 at 1204 2334 3435 4607; bit 10 changes 6 at 12526:0 12700:1 28431:0 28576:1; 11 seen 52, 12 seen 0; end 00DE 0558
Width 512, GPUSTAT 5604200F. T0 mode 0158 target 0100: first read 0D58; IRQ 73 at 874 1674 2508 3276; bit 10 changes 6 at 8959:0 9133:1 41405:0 41550:1; 11 seen 75, 12 seen 0; end 0003 0D58
Width 640, GPUSTAT D606200F. T0 mode 0158 target 0100: first read 0D58; IRQ 92 at 732 1335 1982 2684; bit 10 changes 8 at 13692:0 13866:1 45568:0 45713:1; 11 seen 93, 12 seen 0; end 0044 0558
Done.