===== 01 S1M F16 SIO1 | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
SIO1 MISC (1F80105Ch) read four times before anything else: DFFD DFFD DFFD DFFD
1F8010F8h as found: lw 7FEB1A23, lhu +0 1A23 +2 7FEB, lbu 23 1A EB 7F; 1F8010FCh lw 00FFFFFF
First reads, twice back to back then 1000 cycles on: I_STAT 950D0000 950D0000 950D0000, GPUSTAT
5606200F 5606200F D606200F, SPUSTAT 0005 0005 0005, JOY_STAT 0001D005 00017805 0000D805, DICR 00000000 00000000 00000000
SIO1 with nothing attached; cycles from the TX write; t:v is STAT bits 0-2 (1 TX
ready, 2 RX, 4 TX idle) changing to v at t.
As found: MODE 0000 CTRL 0000 BAUD 0000 STAT 00000185
One byte 55h, MODE 004D BAUD 0088: 55:0 131:1 1462:5 (ready 131, idle 1462)
55h, then AAh written at ready + k tenths of (idle - ready):
 k 0, AAh at 151: 210:0 1512:1 2877:5
 k 1, AAh at 286: 336:0 1519:1 2884:5
 k 2, AAh at 418: 468:0 1515:1 2880:5
 k 3, AAh at 550: 605:0 1516:1 2881:5
 k 4, AAh at 682: 732:0 1524:1 2872:5
 k 5, AAh at 814: 874:0 1513:1 2878:5
 k 6, AAh at 946: 1001:0 1521:1 2886:5
 k 7, AAh at 1078: 1128:0 1512:1 2877:5
 k 8, AAh at 1210: 1260:0 1525:1 2873:5
 k 9, AAh at 1342: 1402:0 1514:1 2879:5
Lengths 5 to 8 bits, 1 stop bit, BAUD 0020, by factor: TX ready/TX idle
 MUL1: 5 bits 55/286; 6 bits 51/286; 7 bits 51/333; 8 bits 51/350;
 MUL16: 5 bits 520/4095; 6 bits 520/4622; 7 bits 524/5119; 8 bits 520/5642;
 MUL64: 5 bits 2050/16386; 6 bits 2054/18435; 7 bits 2054/20487; 8 bits 2050/22540;
Put back: MODE 0000 CTRL 0000 BAUD 0000; MISC now DFFD
Done.