===== 14 COM F16 COM0 COM1 | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
First reads, twice back to back then 1000 cycles on: I_STAT 950D0000 950D0000 950D0000, GPUSTAT
5606200F 5606200F 5606200F, SPUSTAT 0805 0805 0805, JOY_STAT 00013005 0000D805 00006805, DICR 00000000 00000000 00000000
100 turns of an SPU KOFF sh and of a POST (1F802041h) sb, from the cache, warm, under
COM0 0-2, the device's bit 8 set or clear, COM1 0-1, write delay 0-4; the rest as found.
As found: COM_DELAY 00031125, SPU 200931E1, Expansion 2 00070777. Rows: write delay 0-4.
COM0 0 bit 8 1 COM1 0: SPU sh 450 446 531 628 727; POST sb 646 646 646 646 722
COM0 0 bit 8 1 COM1 1: SPU sh 450 446 531 628 727; POST sb 646 646 646 722 820
COM0 0 bit 8 0 COM1 0: SPU sh 450 446 531 628 727; POST sb 646 646 648 646 722
COM0 0 bit 8 0 COM1 1: SPU sh 450 446 531 628 727; POST sb 646 646 646 722 820
COM0 1 bit 8 1 COM1 0: SPU sh 450 446 531 628 727; POST sb 646 646 646 646 722
COM0 1 bit 8 1 COM1 1: SPU sh 450 446 531 628 727; POST sb 646 646 650 722 820
COM0 1 bit 8 0 COM1 0: SPU sh 450 446 531 628 727; POST sb 646 646 646 646 722
COM0 1 bit 8 0 COM1 1: SPU sh 450 446 531 628 727; POST sb 646 646 650 722 820
COM0 2 bit 8 1 COM1 0: SPU sh 450 530 627 726 817; POST sb 646 646 646 728 819
COM0 2 bit 8 1 COM1 1: SPU sh 450 530 627 726 817; POST sb 646 646 728 819 918
COM0 2 bit 8 0 COM1 0: SPU sh 456 446 531 628 727; POST sb 646 646 646 646 722
COM0 2 bit 8 0 COM1 1: SPU sh 450 446 531 628 727; POST sb 646 646 646 722 820
Put back: COM_DELAY 00031125, SPU 200931E1, Expansion 2 00070777
Done.