===== 14 TMR F17 TIMERS AND FRAMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
T0 paused in hblank over 1 to 16 lines at 256 wide; T1 sync 0-3 at three Y ranges; the
640/vres frame; bit 13 after GP1(08h) 27h at 8 points of a frame (row 50, #135, C:92-97).
256 wide 240 lines, range 590-3150 (03GLN's first mode):
 T0 dotclock paused in hblank, over 1 ticks: 255 254 255
 T0 dotclock paused in hblank, over 2 ticks: 510 510 510
 T0 dotclock paused in hblank, over 4 ticks: 1020 1020 1020
 T0 dotclock paused in hblank, over 8 ticks: 2041 2040 2041
 T0 dotclock paused in hblank, over 16 ticks: 4082 4080 4079
 T0 system clock paused in hblank, over 1 ticks: 1614 1613 1613
 T0 system clock paused in hblank, over 2 ticks: 3228 3228 3227
 T0 system clock paused in hblank, over 4 ticks: 6456 6456 6455
 T0 system clock paused in hblank, over 8 ticks: 12910 12911 12912
 T0 system clock paused in hblank, over 16 ticks: 25821 25820 25820
320 wide, Y1 16 Y2 256:
 T1 hblank sync 0 (paused in vblank), IRQ0 to IRQ0: 239 239 239
 T1 hblank sync 1 (reset at vblank), read at IRQ0: 237 237 237
 T1 hblank sync 2 (reset at vblank, counts in it): max 23 min 0, 17 of 19436 reads at max
 T1 hblank sync 3 set after IRQ0: 20000 on, next IRQ0, one after, mode: 0 238 501 263
320 wide, Y1 40 Y2 200:
 T1 hblank sync 0 (paused in vblank), IRQ0 to IRQ0: 159 159 159
 T1 hblank sync 1 (reset at vblank), read at IRQ0: 157 157 157
 T1 hblank sync 2 (reset at vblank, counts in it): max 95 min 0, 16 of 19240 reads at max
 T1 hblank sync 3 set after IRQ0: 20000 on, next IRQ0, one after, mode: 0 158 421 263
320 wide, Y1 100 Y2 110:
 T1 hblank sync 0 (paused in vblank), IRQ0 to IRQ0: 9 9 9
 T1 hblank sync 1 (reset at vblank), read at IRQ0: 7 7 7
 T1 hblank sync 2 (reset at vblank, counts in it): max 246 min 0, 17 of 18836 reads at max
 T1 hblank sync 3 set after IRQ0: 20000 on, next IRQ0, one after, mode: 0 8 271 263
640 wide, GP1(08h) 03h (reference):
 cycles IRQ0 to IRQ0: 435027 369462 435010 500708 500540 435009
 hblank ticks: 263 263 263 263 263 263
 GPUSTAT at IRQ0: 14062518 14062518 14062518 14062518 14062518 14062518
640 wide, vertical resolution bit set, interlace off, GP1(08h) 07h:
 cycles IRQ0 to IRQ0: 565002 564921 564915 565015 564897 565054
 hblank ticks: 0 0 0 0 0 0
 GPUSTAT at IRQ0: 140E0518 140E0518 140E0518 140E0518 140E0518 140E0518
640 wide, vertical resolution bit set, interlace on, GP1(08h) 27h:
 cycles IRQ0 to IRQ0: 566123 564058 566013 564076 566123 563932
 hblank ticks: 263 262 263 262 263 262
 GPUSTAT at IRQ0: 144E0518 144E2518 144E0518 144E2518 144E0518 144E2518
GP1(08h) 27h written p*70000 cycles after an IRQ0 from 03h: GPUSTAT bit 13 at once, then
at the next four IRQ0s; three runs:
p 0: 0/1010 0/1010 0/1010
p 1: 0/0101 1/1010 0/0101
p 2: 1/1010 0/0101 1/1010
p 3: 0/0101 1/1010 0/0101
p 4: 1/1010 0/0101 1/1010
p 5: 0/0101 1/1010 0/0101
p 6: 1/1010 0/0101 1/1010
p 7: 0/0101 1/1010 0/0101
Done.