===== 03 IMT F27 IMASK UPPER AFTER TIMERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
I_MASK's upper half after sw 12345678h, lw of a timer register, the read; cold / warm, two
runs each; a as IMU, b and c with marked words after the access (row 57; IMU l 03E0/3C03).
timer 0 counter: a 0000/2610 0000/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
timer 0 mode: a 2C00/2610 2C00/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
timer 0 target: a 2C00/2610 2C00/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
timer 1 counter: a 2C00/2610 2C00/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
timer 1 mode: a 2C00/2610 2C00/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
timer 1 target: a 2C00/2610 2C00/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
timer 2 counter: a 2C00/2610 2C00/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
timer 2 mode: a 2C00/2610 2C00/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
timer 2 target: a 2C00/2610 2C00/2610 b 3400/2610 3400/2610 c 2C00/2610 2C00/2610
Done.