===== 03 PLW F29 PULSE BIT 10 LOW | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Row 96. Pulse mode, system clock, target 0100h; 448 mode reads from the mode write
(timers.txt:26-36). Modes: 0010h one-shot, 0018h one-shot reset at target, 0030h one-shot
at target or FFFFh, 0050h repeat, 0058h repeat reset at target. read:bit 10.
T0 0010: 3192 cycles for 448 reads (7.12 each), I_STAT bit 4 1, first 0410; (0 changes)
T0 0018: 3192 cycles for 448 reads (7.12 each), I_STAT bit 4 1, first 0418; (0 changes)
T0 0030: 3192 cycles for 448 reads (7.12 each), I_STAT bit 4 1, first 0430; (0 changes)
T0 0050: 3192 cycles for 448 reads (7.12 each), I_STAT bit 4 1, first 0450; (0 changes)
T0 0058: 3193 cycles for 448 reads (7.12 each), I_STAT bit 4 1, first 0458; 109:0 110:1 218:0 219:1 363:0 364:1 (6 changes)
T1 0010: 3188 cycles for 448 reads (7.11 each), I_STAT bit 5 1, first 0410; (0 changes)
T1 0018: 3189 cycles for 448 reads (7.11 each), I_STAT bit 5 1, first 0418; (0 changes)
T1 0030: 3188 cycles for 448 reads (7.11 each), I_STAT bit 5 1, first 0430; (0 changes)
T1 0050: 3189 cycles for 448 reads (7.11 each), I_STAT bit 5 1, first 0450; (0 changes)
T1 0058: 3189 cycles for 448 reads (7.11 each), I_STAT bit 5 1, first 0458; 109:0 110:1 218:0 219:1 363:0 364:1 (6 changes)
T2 0010: 3190 cycles for 448 reads (7.12 each), I_STAT bit 6 1, first 0410; (0 changes)
T2 0018: 3190 cycles for 448 reads (7.12 each), I_STAT bit 6 1, first 0418; (0 changes)
T2 0030: 3190 cycles for 448 reads (7.12 each), I_STAT bit 6 1, first 0430; (0 changes)
T2 0050: 3190 cycles for 448 reads (7.12 each), I_STAT bit 6 1, first 0450; (0 changes)
T2 0058: 3190 cycles for 448 reads (7.12 each), I_STAT bit 6 1, first 0458; 109:0 110:1 254:0 255:1 363:0 364:1 (6 changes)
Done.