===== 04 F8C F29 1F8010F8 BY CHANNEL | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Row 59. 1F8010F8h and 1F8010FCh (dma/channels.txt:132-141) by lw after each step.
As the group starts, before anything here: F8 7FE72A23 FC 00FFFFFF
The image at 28000h uploaded and read back: 0 halfwords of 512 differ.
After the SPU set up (DMA4 write and read of 256 words): F8 7FEB0A63 FC 00FFFFFF
After DMA0, a quant table of 16 words: F8 7FEF1AA0 FC 00FFFFFF
After DMA0, a scale table of 32 words: F8 7FEF1AA0 FC 00FFFFFF
DMA0 done, DMA1 done.
After DMA1, 16 words of one 8 bit block (and DMA0's 32 words): F8 3FF32AC1 FC 00FFFFFF
After a DMA2 list of 16 empty nodes: F8 3FF33A0A FC 00FFFFFF
After a DMA4 write of 16 words: F8 3FF30A53 FC 00FFFFFF
After a DMA4 read of 16 words: F8 3FF30A53 FC 00FFFFFF
After DMA5, 1 word with bit 28: F8 3BF41C9C FC 00FFFFFF
After a DMA6 OTC of 256 words: F8 3BE0ACE5 FC 00FFFFFF
A DMA6 OTC of 4096 words, read straight after its CHCR write: F8 3AE0ACE5, MADR6 00123C7C, F8
3BE0ACE5, CHCR6 00000002
After it: F8 3BE0ACE5 FC 00FFFFFF
DPCR written its own value: F8 3BE0ACE5 FC 00FFFFFF
DPCR written 00000000: F8 3BE0ACE5 FC 00FFFFFF
DPCR written 07654321 (every enable off): F8 0BE0ACE5 FC 00FFFFFF
DPCR written back: F8 3BE0ACE5 FC 00FFFFFF
DICR written 00000000: F8 3BE0ACE5 FC 00FFFFFF
DICR written 007F0000 (enables, no master): F8 3BE0ACE5 FC 00FFFFFF
DICR written 00800000 (master alone): F8 3BE0ACE5 FC 00FFFFFF
DICR written back, flags acknowledged: F8 3BE0ACE5 FC 00FFFFFF
Done.